JPS5696553A - Code conversion circuit - Google Patents

Code conversion circuit

Info

Publication number
JPS5696553A
JPS5696553A JP17255179A JP17255179A JPS5696553A JP S5696553 A JPS5696553 A JP S5696553A JP 17255179 A JP17255179 A JP 17255179A JP 17255179 A JP17255179 A JP 17255179A JP S5696553 A JPS5696553 A JP S5696553A
Authority
JP
Japan
Prior art keywords
output
fed
conversion circuit
memory
code conversion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17255179A
Other languages
Japanese (ja)
Inventor
Koichi Inoue
Eiichiro Murata
Manabu Yamane
Tetsuaki Nakanishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP17255179A priority Critical patent/JPS5696553A/en
Publication of JPS5696553A publication Critical patent/JPS5696553A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M5/00—Conversion of the form of the representation of individual digits

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To realize the combination of a number of codes with a comparatively simple circuit, by using the output of an exclusive logical sum gate for the address designation of memory via a shift register and decoder. CONSTITUTION:An input signal is fed to one input of an exclusive logical sum gate 1, the output is fed to a 8-bit shift register 2, and the output of, e.g., 3 prestages of the register 2 is fed to a decoder 3. Further, the output decoded into 8 signals designates the address of a bit memory 4, and the output of the memory 4 is fed to another input of the gate 1. Thus, the combination of codes in 14336 ways can be made.
JP17255179A 1979-12-28 1979-12-28 Code conversion circuit Pending JPS5696553A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17255179A JPS5696553A (en) 1979-12-28 1979-12-28 Code conversion circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17255179A JPS5696553A (en) 1979-12-28 1979-12-28 Code conversion circuit

Publications (1)

Publication Number Publication Date
JPS5696553A true JPS5696553A (en) 1981-08-04

Family

ID=15943956

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17255179A Pending JPS5696553A (en) 1979-12-28 1979-12-28 Code conversion circuit

Country Status (1)

Country Link
JP (1) JPS5696553A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100763533B1 (en) 2006-06-01 2007-10-05 삼성전자주식회사 Bus inverting code generating apparatus and method of generating bus inverting code using the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100763533B1 (en) 2006-06-01 2007-10-05 삼성전자주식회사 Bus inverting code generating apparatus and method of generating bus inverting code using the same

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