JPS5689144A - Asynchronous type data receiving device - Google Patents

Asynchronous type data receiving device

Info

Publication number
JPS5689144A
JPS5689144A JP16485579A JP16485579A JPS5689144A JP S5689144 A JPS5689144 A JP S5689144A JP 16485579 A JP16485579 A JP 16485579A JP 16485579 A JP16485579 A JP 16485579A JP S5689144 A JPS5689144 A JP S5689144A
Authority
JP
Japan
Prior art keywords
signal
error
clock
receiving device
data receiving
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16485579A
Other languages
Japanese (ja)
Other versions
JPS6316934B2 (en
Inventor
Toshinori Mori
Kyoichi Iwasa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP16485579A priority Critical patent/JPS5689144A/en
Publication of JPS5689144A publication Critical patent/JPS5689144A/en
Publication of JPS6316934B2 publication Critical patent/JPS6316934B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0079—Receiver details
    • H04L7/0083—Receiver details taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Communication Control (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Dc Digital Transmission (AREA)

Abstract

PURPOSE:To prevent an error from affecting following other frames, by using only the signal in one frame to perform frame detection and by restraining the error caused by noise to the error in one frame. CONSTITUTION:Clock (b) extracted by decoder 4 is delayed in delay line 10 by the 1/2 of the clock period and becomes signal (e). Next, NOR between clock (b) and signal (e) is operated by NOR circuit 11 to obtain signal (f) which is low-level during outputting of clocks and is high-level during outputting of no clocks. Signal (f) is used as the timing signal to take data into latch circuit 6. Data (g) is output to output terminal 7 of circuit 6. As a result, even if noise is generated, the error is prevented from affecting other frames.
JP16485579A 1979-12-20 1979-12-20 Asynchronous type data receiving device Granted JPS5689144A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16485579A JPS5689144A (en) 1979-12-20 1979-12-20 Asynchronous type data receiving device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16485579A JPS5689144A (en) 1979-12-20 1979-12-20 Asynchronous type data receiving device

Publications (2)

Publication Number Publication Date
JPS5689144A true JPS5689144A (en) 1981-07-20
JPS6316934B2 JPS6316934B2 (en) 1988-04-12

Family

ID=15801189

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16485579A Granted JPS5689144A (en) 1979-12-20 1979-12-20 Asynchronous type data receiving device

Country Status (1)

Country Link
JP (1) JPS5689144A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59105740A (en) * 1982-11-22 1984-06-19 ウエスターン　エレクトリック　カムパニー，インコーポレーテッド Asynchronous binary data communication system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59105740A (en) * 1982-11-22 1984-06-19 ウエスターン　エレクトリック　カムパニー，インコーポレーテッド Asynchronous binary data communication system
JPH04103743U (en) * 1982-11-22 1992-09-07 ウエスターン エレクトリツク カムパニー，インコーポレーテツド Asynchronous binary data communication circuit

Also Published As

Publication number Publication date
JPS6316934B2 (en) 1988-04-12

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