JPS5671893A - Control system for memory error - Google Patents

Control system for memory error

Info

Publication number
JPS5671893A
JPS5671893A JP14615879A JP14615879A JPS5671893A JP S5671893 A JPS5671893 A JP S5671893A JP 14615879 A JP14615879 A JP 14615879A JP 14615879 A JP14615879 A JP 14615879A JP S5671893 A JPS5671893 A JP S5671893A
Authority
JP
Japan
Prior art keywords
clock pulse
low level
parity
memory
operation time
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14615879A
Other languages
Japanese (ja)
Inventor
Jiro Shiohama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP14615879A priority Critical patent/JPS5671893A/en
Publication of JPS5671893A publication Critical patent/JPS5671893A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To decrease the number of system down times unnecessary and to increase the system operation time, by temporarily extending the memory readout and repeating the retrial to the parity error generation due to temporary noise.
CONSTITUTION: When an impulse noise is input tentatively, the parity error is detected at the parity detection circuit 4 and the parity monitor signal 10 is a waveform as a low level l15. When this low level is input to a system clock pulse generating circuit 6, no frequency division is made at 17 of (b) at the leading pulse 16 of (a), and the system clock pulse keeps high level with the timing 13 of this low level l. In this case, the clock pulse is extended for one period of the clock pulse of (a) and the readout of memory is again made by this. Then, the number of system down times is decreased and the system operation time can be increased.
COPYRIGHT: (C)1981,JPO&Japio
JP14615879A 1979-11-12 1979-11-12 Control system for memory error Pending JPS5671893A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14615879A JPS5671893A (en) 1979-11-12 1979-11-12 Control system for memory error

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14615879A JPS5671893A (en) 1979-11-12 1979-11-12 Control system for memory error

Publications (1)

Publication Number Publication Date
JPS5671893A true JPS5671893A (en) 1981-06-15

Family

ID=15401435

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14615879A Pending JPS5671893A (en) 1979-11-12 1979-11-12 Control system for memory error

Country Status (1)

Country Link
JP (1) JPS5671893A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59178692A (en) * 1983-03-29 1984-10-09 Fujitsu Ltd Information processing device
JPH02242342A (en) * 1989-03-15 1990-09-26 Fujitsu Ltd Error avoiding method for data
JPH0496846A (en) * 1990-08-13 1992-03-30 Fujitsu Ltd Portable terminal device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59178692A (en) * 1983-03-29 1984-10-09 Fujitsu Ltd Information processing device
JPH02242342A (en) * 1989-03-15 1990-09-26 Fujitsu Ltd Error avoiding method for data
JPH0496846A (en) * 1990-08-13 1992-03-30 Fujitsu Ltd Portable terminal device

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