JPS567149A - Interruption control method - Google Patents

Interruption control method

Info

Publication number
JPS567149A
JPS567149A JP8202379A JP8202379A JPS567149A JP S567149 A JPS567149 A JP S567149A JP 8202379 A JP8202379 A JP 8202379A JP 8202379 A JP8202379 A JP 8202379A JP S567149 A JPS567149 A JP S567149A
Authority
JP
Japan
Prior art keywords
interruption
memory
action
address
contents
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8202379A
Other languages
Japanese (ja)
Inventor
Yoshihisa Shibata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP8202379A priority Critical patent/JPS567149A/en
Publication of JPS567149A publication Critical patent/JPS567149A/en
Pending legal-status Critical Current

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  • Detection And Correction Of Errors (AREA)

Abstract

PURPOSE: To secure the normal continuation of the interruption process without causing any system breakdown, by setting forcedly all bits to "on" in case the parity error is detected in the read contents of the interruption request register memory.
CONSTITUTION: Interruption request register memory 300 in the transfer device is always scanned, and the interruption action is given to the CPU by referring the information of the memory region corresponding to channel control unit 200 when the bit reads out the contents of "1". In case the parity error is detected in the read contents of memory 300 at the request register time or the scanning time to memory 300, control circuit 320 gives the indication to write "all 1" to partial writing circuit 330 through bus 408. Then "all 1" is written to the address shown by address register 340, i.e., the address that has just been read out. Accordingly, the interruption request can always be found out by scanning action to perform the interruption action at all times. Thus the alteration has been given so as to secure the normal operation for the device as a whole. And accordingly, the worst fault such as the system breakdown or the like can be avoided.
COPYRIGHT: (C)1981,JPO&Japio
JP8202379A 1979-06-30 1979-06-30 Interruption control method Pending JPS567149A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8202379A JPS567149A (en) 1979-06-30 1979-06-30 Interruption control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8202379A JPS567149A (en) 1979-06-30 1979-06-30 Interruption control method

Publications (1)

Publication Number Publication Date
JPS567149A true JPS567149A (en) 1981-01-24

Family

ID=13762921

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8202379A Pending JPS567149A (en) 1979-06-30 1979-06-30 Interruption control method

Country Status (1)

Country Link
JP (1) JPS567149A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02151936A (en) * 1988-11-28 1990-06-11 Internatl Business Mach Corp <Ibm> Error processing for change bit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02151936A (en) * 1988-11-28 1990-06-11 Internatl Business Mach Corp <Ibm> Error processing for change bit

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