JPS5661087A - Control system for dynamic memory - Google Patents

Control system for dynamic memory

Info

Publication number
JPS5661087A
JPS5661087A JP13725479A JP13725479A JPS5661087A JP S5661087 A JPS5661087 A JP S5661087A JP 13725479 A JP13725479 A JP 13725479A JP 13725479 A JP13725479 A JP 13725479A JP S5661087 A JPS5661087 A JP S5661087A
Authority
JP
Japan
Prior art keywords
memory
crt
cycle
refresh
dynamic memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13725479A
Other languages
Japanese (ja)
Other versions
JPS5939838B2 (en
Inventor
Takatoshi Ishii
Akiji Mie
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP54137254A priority Critical patent/JPS5939838B2/en
Publication of JPS5661087A publication Critical patent/JPS5661087A/en
Publication of JPS5939838B2 publication Critical patent/JPS5939838B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1636—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement using refresh
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/26—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using discharge tubes
    • G11C11/30—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using discharge tubes using vacuum tubes

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)

Abstract

PURPOSE:To make exclusive refresh circuit unnecessary, by assigning the refresh cycle of dynamic memory in the idle time of periodical access. CONSTITUTION:In the CRT memory cycle (SCRT=1) when the display period signal DTM=1, CRT memory addresses M06-M00 (row address) and CRT memory addresses M13-M07 (column address) are sequentially output from a memory address selector 3. Thus, a CRT controller 2 accesses V-RAM of a dynamic memory 8, allowing to surely refresh the corresponded picture information. On the other hand, in a CPU memory cycle (SCRT=0), CPU memory addresses A13- A07 (column address) are sequentially output from the selector 3, and a CPU1 can access to V-RAM of the memory 8 and other areas.
JP54137254A 1979-10-24 1979-10-24 Dynamic memory control method Expired JPS5939838B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP54137254A JPS5939838B2 (en) 1979-10-24 1979-10-24 Dynamic memory control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54137254A JPS5939838B2 (en) 1979-10-24 1979-10-24 Dynamic memory control method

Publications (2)

Publication Number Publication Date
JPS5661087A true JPS5661087A (en) 1981-05-26
JPS5939838B2 JPS5939838B2 (en) 1984-09-26

Family

ID=15194357

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54137254A Expired JPS5939838B2 (en) 1979-10-24 1979-10-24 Dynamic memory control method

Country Status (1)

Country Link
JP (1) JPS5939838B2 (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58182193A (en) * 1982-04-19 1983-10-25 Toshiba Corp Refresh controller
JPS5968893A (en) * 1982-10-13 1984-04-18 Fujitsu Ltd Memory control system
JPS59101089A (en) * 1982-11-30 1984-06-11 Shimadzu Corp Memory circuit
JPS60211697A (en) * 1984-04-05 1985-10-24 Matsushita Electric Ind Co Ltd Address generator for refreshing dynamic ram
JPH03129391A (en) * 1990-06-15 1991-06-03 Hitachi Ltd Access method for refresh memory, display controller and graphic processor
JPH03267885A (en) * 1990-03-16 1991-11-28 Pfu Ltd Video special effect processing system
JPH05114286A (en) * 1982-09-29 1993-05-07 Texas Instr Inc <Ti> Electronic device
JPH07225573A (en) * 1995-01-26 1995-08-22 Hitachi Ltd Method of accessing refresh memory, display controller and graphic processor

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58182193A (en) * 1982-04-19 1983-10-25 Toshiba Corp Refresh controller
JPH0474797B2 (en) * 1982-04-19 1992-11-27
JPH05114286A (en) * 1982-09-29 1993-05-07 Texas Instr Inc <Ti> Electronic device
JPS5968893A (en) * 1982-10-13 1984-04-18 Fujitsu Ltd Memory control system
JPS59101089A (en) * 1982-11-30 1984-06-11 Shimadzu Corp Memory circuit
JPS60211697A (en) * 1984-04-05 1985-10-24 Matsushita Electric Ind Co Ltd Address generator for refreshing dynamic ram
JPH03267885A (en) * 1990-03-16 1991-11-28 Pfu Ltd Video special effect processing system
JPH03129391A (en) * 1990-06-15 1991-06-03 Hitachi Ltd Access method for refresh memory, display controller and graphic processor
JPH07225573A (en) * 1995-01-26 1995-08-22 Hitachi Ltd Method of accessing refresh memory, display controller and graphic processor

Also Published As

Publication number Publication date
JPS5939838B2 (en) 1984-09-26

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