JPS5654532A - Initializing method for main memory device - Google Patents

Initializing method for main memory device

Info

Publication number
JPS5654532A
JPS5654532A JP13001479A JP13001479A JPS5654532A JP S5654532 A JPS5654532 A JP S5654532A JP 13001479 A JP13001479 A JP 13001479A JP 13001479 A JP13001479 A JP 13001479A JP S5654532 A JPS5654532 A JP S5654532A
Authority
JP
Japan
Prior art keywords
parity
main memory
error
circuit
decoder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13001479A
Other languages
Japanese (ja)
Inventor
Manabu Araoka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP13001479A priority Critical patent/JPS5654532A/en
Publication of JPS5654532A publication Critical patent/JPS5654532A/en
Pending legal-status Critical Current

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  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE: To initialize a volatile memory in electric power recovery without destroying the contents of a nonvolatile memory by inhibiting transmission of a parity error to a main memory device while the initialization is in process.
CONSTITUTION: In data processor 8 for recovery processing of an electric power break, the output of decoder 9 controlling arithmetic circuit 10 sets flip-flop 11. This set signal is applied as a parity-error detection inhibition signal to gate 4 of main memory unit 1. Readout data from main memory cell 2 consisting of volatile and nonvolatile memories is sent to data processor 8 via parity circuit 3, but while the above-mentioned parity-error detection inhibition signal appears, an error signal is not sent to processor 8. When an error occurs, on the other hand, parity circuit 3 sets a correct parity bit and rewrites main memory cell 2. After the above-mentioned initialization, decoder 9 resets FF11 and places the processing operation in a normal state.
COPYRIGHT: (C)1981,JPO&Japio
JP13001479A 1979-10-11 1979-10-11 Initializing method for main memory device Pending JPS5654532A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13001479A JPS5654532A (en) 1979-10-11 1979-10-11 Initializing method for main memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13001479A JPS5654532A (en) 1979-10-11 1979-10-11 Initializing method for main memory device

Publications (1)

Publication Number Publication Date
JPS5654532A true JPS5654532A (en) 1981-05-14

Family

ID=15024013

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13001479A Pending JPS5654532A (en) 1979-10-11 1979-10-11 Initializing method for main memory device

Country Status (1)

Country Link
JP (1) JPS5654532A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04155541A (en) * 1990-10-19 1992-05-28 Fujitsu Ltd Memory parity error controlling method and parity error controller and channel device
US5696917A (en) * 1994-06-03 1997-12-09 Intel Corporation Method and apparatus for performing burst read operations in an asynchronous nonvolatile memory

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4861035A (en) * 1971-12-02 1973-08-27
JPS5268330A (en) * 1975-12-05 1977-06-07 Hitachi Ltd Initializing system of memory
JPS52124836A (en) * 1976-04-13 1977-10-20 Mitsubishi Electric Corp Reset of data processing unit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4861035A (en) * 1971-12-02 1973-08-27
JPS5268330A (en) * 1975-12-05 1977-06-07 Hitachi Ltd Initializing system of memory
JPS52124836A (en) * 1976-04-13 1977-10-20 Mitsubishi Electric Corp Reset of data processing unit

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04155541A (en) * 1990-10-19 1992-05-28 Fujitsu Ltd Memory parity error controlling method and parity error controller and channel device
US5696917A (en) * 1994-06-03 1997-12-09 Intel Corporation Method and apparatus for performing burst read operations in an asynchronous nonvolatile memory
US6026465A (en) * 1994-06-03 2000-02-15 Intel Corporation Flash memory including a mode register for indicating synchronous or asynchronous mode of operation
US6564285B1 (en) 1994-06-03 2003-05-13 Intel Corporation Synchronous interface for a nonvolatile memory

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