JPS5647841A - Pcm signal operation system - Google Patents

Pcm signal operation system

Info

Publication number
JPS5647841A
JPS5647841A JP12158079A JP12158079A JPS5647841A JP S5647841 A JPS5647841 A JP S5647841A JP 12158079 A JP12158079 A JP 12158079A JP 12158079 A JP12158079 A JP 12158079A JP S5647841 A JPS5647841 A JP S5647841A
Authority
JP
Japan
Prior art keywords
pcm
digital memory
pcm signal
operation system
signal operation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12158079A
Other languages
Japanese (ja)
Inventor
Yoshikazu Ikeda
Yasushi Wakahara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
KDDI Corp
Original Assignee
Kokusai Denshin Denwa KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kokusai Denshin Denwa KK filed Critical Kokusai Denshin Denwa KK
Priority to JP12158079A priority Critical patent/JPS5647841A/en
Priority to GB8030171A priority patent/GB2059123B/en
Priority to US06/189,539 priority patent/US4357674A/en
Publication of JPS5647841A publication Critical patent/JPS5647841A/en
Pending legal-status Critical Current

Links

Landscapes

  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Transmission Systems Not Characterized By The Medium Used For Transmission (AREA)

Abstract

PURPOSE: To directly perform the operation of PCM by use of a digital memory which has recorded the operation results as to all the combinations of inputs.
CONSTITUTION: This each PCM signal P, Q is made an address input as to two PCM signal inputs P, Q, and a digital memory 30 which reads out its contents is provided. The digital memory 30 stores the operation results as to all the combinations of PCM signals P, Q of 8 bits to be input. The aforesaid operation results are read out by inputting the PCM signals P, Q as address. Accordingly, the operation output R can be directly received from the digital memory 30 to the output 20.
COPYRIGHT: (C)1981,JPO&Japio
JP12158079A 1979-09-22 1979-09-22 Pcm signal operation system Pending JPS5647841A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP12158079A JPS5647841A (en) 1979-09-22 1979-09-22 Pcm signal operation system
GB8030171A GB2059123B (en) 1979-09-22 1980-09-18 Pcm signal calculator
US06/189,539 US4357674A (en) 1979-09-22 1980-09-22 PCM Signal calculator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12158079A JPS5647841A (en) 1979-09-22 1979-09-22 Pcm signal operation system

Publications (1)

Publication Number Publication Date
JPS5647841A true JPS5647841A (en) 1981-04-30

Family

ID=14814753

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12158079A Pending JPS5647841A (en) 1979-09-22 1979-09-22 Pcm signal operation system

Country Status (1)

Country Link
JP (1) JPS5647841A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5814252A (en) * 1981-07-16 1983-01-27 Mitsubishi Electric Corp Digital addition circuit
JPS5852747A (en) * 1981-09-25 1983-03-29 Nec Corp Adding and subtracting circuit
JPS58107628U (en) * 1982-01-12 1983-07-22 日立工機株式会社 Data code converter
JPS59180632A (en) * 1983-03-31 1984-10-13 Toshiba Corp Arithmetic unit
JPS59184942A (en) * 1983-04-05 1984-10-20 Fuji Xerox Co Ltd Kanji code converting method
JPS6136839A (en) * 1984-07-30 1986-02-21 Aisuke Katayama Parallel compensation system for high-speed multiplication with code
JPS63183148U (en) * 1987-05-18 1988-11-25

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5814252A (en) * 1981-07-16 1983-01-27 Mitsubishi Electric Corp Digital addition circuit
JPS5852747A (en) * 1981-09-25 1983-03-29 Nec Corp Adding and subtracting circuit
JPH0225538B2 (en) * 1981-09-25 1990-06-04 Nippon Electric Co
JPS58107628U (en) * 1982-01-12 1983-07-22 日立工機株式会社 Data code converter
JPS59180632A (en) * 1983-03-31 1984-10-13 Toshiba Corp Arithmetic unit
JPS59184942A (en) * 1983-04-05 1984-10-20 Fuji Xerox Co Ltd Kanji code converting method
JPH0516605B2 (en) * 1983-04-05 1993-03-04 Fuji Xerox Co Ltd
JPS6136839A (en) * 1984-07-30 1986-02-21 Aisuke Katayama Parallel compensation system for high-speed multiplication with code
JPS63183148U (en) * 1987-05-18 1988-11-25

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