JPS5644919A - Control board - Google Patents

Control board

Info

Publication number
JPS5644919A
JPS5644919A JP12069479A JP12069479A JPS5644919A JP S5644919 A JPS5644919 A JP S5644919A JP 12069479 A JP12069479 A JP 12069479A JP 12069479 A JP12069479 A JP 12069479A JP S5644919 A JPS5644919 A JP S5644919A
Authority
JP
Japan
Prior art keywords
cpu
controlled
control board
dct
board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12069479A
Other languages
Japanese (ja)
Inventor
Hiroyuki Ueda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP12069479A priority Critical patent/JPS5644919A/en
Publication of JPS5644919A publication Critical patent/JPS5644919A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To make it unnecessary to provide a timer for each controlled memory board, by storing individual access times of controlled memory boards in the ROM of the control board and by generating WAIT signals for them by the control board, in the small-scale computer equipped with a CPU.
CONSTITUTION: The CPU transmits the address signal indicating memory board HCB-n to the system bus. The ROM in control board CB transmits storage data, which corresponds to the data read time in the designated memory board to be controlled, to down counter DCT. DCT not only sets access time information but also transmits the WAIT signal to the CPU. When the count value of DCT becomes 0 by clocks of clock generator CG and the WAIT signal terminals, the CPU starts data read from memory board to be controlled HCB-n.
COPYRIGHT: (C)1981,JPO&Japio
JP12069479A 1979-09-21 1979-09-21 Control board Pending JPS5644919A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12069479A JPS5644919A (en) 1979-09-21 1979-09-21 Control board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12069479A JPS5644919A (en) 1979-09-21 1979-09-21 Control board

Publications (1)

Publication Number Publication Date
JPS5644919A true JPS5644919A (en) 1981-04-24

Family

ID=14792649

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12069479A Pending JPS5644919A (en) 1979-09-21 1979-09-21 Control board

Country Status (1)

Country Link
JP (1) JPS5644919A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58125135A (en) * 1982-01-19 1983-07-26 Mitsubishi Electric Corp Process data input and output device
JPS6182258A (en) * 1984-09-29 1986-04-25 Ricoh Elemex Corp Input/output device
EP0511408A1 (en) * 1990-11-20 1992-11-04 Oki Electric Industry Company, Limited Synchronous semiconductor memory
US5287327A (en) * 1990-11-20 1994-02-15 Oki Electric Industry Co., Ltd. Synchronous dynamic random access memory
JPH07160629A (en) * 1993-12-10 1995-06-23 Nec Corp Microprocessor
US5572706A (en) * 1984-01-20 1996-11-05 Canon Kabushiki Kaisha Electronic equipment having controllable access times for detachable cartridges

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58125135A (en) * 1982-01-19 1983-07-26 Mitsubishi Electric Corp Process data input and output device
US5572706A (en) * 1984-01-20 1996-11-05 Canon Kabushiki Kaisha Electronic equipment having controllable access times for detachable cartridges
JPS6182258A (en) * 1984-09-29 1986-04-25 Ricoh Elemex Corp Input/output device
EP0511408A1 (en) * 1990-11-20 1992-11-04 Oki Electric Industry Company, Limited Synchronous semiconductor memory
US5287327A (en) * 1990-11-20 1994-02-15 Oki Electric Industry Co., Ltd. Synchronous dynamic random access memory
US5311483A (en) * 1990-11-20 1994-05-10 Oki Electric Industry Co., Ltd. Synchronous type semiconductor memory
US5339276A (en) * 1990-11-20 1994-08-16 Oki Electric Industry Co., Ltd. Synchronous dynamic random access memory
US5430688A (en) * 1990-11-20 1995-07-04 Oki Electric Industry Co., Ltd. Synchronous dynamic random access memory
US5521879A (en) * 1990-11-20 1996-05-28 Oki Electric Industry Co., Ltd. Synchronous dynamic random acess memory
JPH07160629A (en) * 1993-12-10 1995-06-23 Nec Corp Microprocessor

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