JPS5619263A - Waveform shaping circuit - Google Patents

Waveform shaping circuit

Info

Publication number
JPS5619263A
JPS5619263A JP9517079A JP9517079A JPS5619263A JP S5619263 A JPS5619263 A JP S5619263A JP 9517079 A JP9517079 A JP 9517079A JP 9517079 A JP9517079 A JP 9517079A JP S5619263 A JPS5619263 A JP S5619263A
Authority
JP
Japan
Prior art keywords
signal
phase
division
compensator
clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9517079A
Other languages
Japanese (ja)
Inventor
Toshiya Senoo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Meidensha Electric Manufacturing Co Ltd
Original Assignee
Meidensha Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Meidensha Electric Manufacturing Co Ltd filed Critical Meidensha Electric Manufacturing Co Ltd
Priority to JP9517079A priority Critical patent/JPS5619263A/en
Publication of JPS5619263A publication Critical patent/JPS5619263A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/20—Repeater circuits; Relay circuits
    • H04L25/24—Relay circuits using discharge tubes or semiconductor devices
    • H04L25/242—Relay circuits using discharge tubes or semiconductor devices with retiming
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
  • Dc Digital Transmission (AREA)
  • Small-Scale Networks (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To give a shaping to the signal having a large waveform distortion into the signal having the prescribed pulse duration, by carrying out a phase comparation between the input signal and the received clock at the changing point of the input signal and thus securing the synchronism of the digital phase. CONSTITUTION:Phase comparator 1 carries out a phase comparison to received clock (d) at the fall point of input signal (c), and then transmits phase comparison signal S1 to phase compensator 3. And phase compensation controller 2 transmits phase compensation timing signal s2 produced by the fall of signal (c) and the rise of signal (d) each to compensator 3. Compensator 3 gives the 1/4 division to the output of reference frequency oscillator 6 while receiving no signal s2. And the 1/4 division is changed over to the 1/3 division when receiving signal s2 and advance commanding signal s1. Furthermore, the 1/3 division is changed over to the 1/5 division with reception of both signal s2 and delay commanding signal s1. Then the 1/32 phase comensation is carried out for signal (d), and thus phase compensation signal s3 is sent to divider 4. Signal s3 is divided into 1/8 by divider 4 to produce reception clock (d) synchronized with signal (c). Clock (d) is then sent to waveform shaping circuit 5, and signal (c) is sampled by signal (d) at circuit 5. Then waveform shaping output signal (e) having the prescribed pulse duration is transmitted.
JP9517079A 1979-07-26 1979-07-26 Waveform shaping circuit Pending JPS5619263A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9517079A JPS5619263A (en) 1979-07-26 1979-07-26 Waveform shaping circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9517079A JPS5619263A (en) 1979-07-26 1979-07-26 Waveform shaping circuit

Publications (1)

Publication Number Publication Date
JPS5619263A true JPS5619263A (en) 1981-02-23

Family

ID=14130281

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9517079A Pending JPS5619263A (en) 1979-07-26 1979-07-26 Waveform shaping circuit

Country Status (1)

Country Link
JP (1) JPS5619263A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60253344A (en) * 1984-03-20 1985-12-14 エヌ・ベ−・フイリツプス・フル−イランペンフアブリケン Method of synchronizing with clock out of network and synchronizing circuit disposition
JPS6184941A (en) * 1984-10-03 1986-04-30 Hitachi Ltd Clock synchronizing system in transmission system
JPS61209155A (en) * 1985-03-13 1986-09-17 ダイアホイルヘキスト株式会社 Composite film
JPS62112435A (en) * 1985-11-12 1987-05-23 Nec Corp Signal decoder
JPS62117138A (en) * 1985-10-29 1987-05-28 Teijin Ltd Magnetic recording tape
JPH01161936A (en) * 1987-11-19 1989-06-26 American Teleph & Telegr Co <Att> Clock recovery apparatus using digital pll
JPH01264828A (en) * 1988-04-18 1989-10-23 Toyobo Co Ltd Biaxially oriented polyester film
JPH057925U (en) * 1991-07-12 1993-02-02 株式会社クボタ Water cooling system for forced circulation type water cooling engine

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60253344A (en) * 1984-03-20 1985-12-14 エヌ・ベ−・フイリツプス・フル−イランペンフアブリケン Method of synchronizing with clock out of network and synchronizing circuit disposition
JPS6184941A (en) * 1984-10-03 1986-04-30 Hitachi Ltd Clock synchronizing system in transmission system
JPS61209155A (en) * 1985-03-13 1986-09-17 ダイアホイルヘキスト株式会社 Composite film
JPH0468144B2 (en) * 1985-03-13 1992-10-30 Daiafoil
JPS62117138A (en) * 1985-10-29 1987-05-28 Teijin Ltd Magnetic recording tape
JPH0668825B2 (en) * 1985-10-29 1994-08-31 帝人株式会社 Magnetic recording tape
JPS62112435A (en) * 1985-11-12 1987-05-23 Nec Corp Signal decoder
JPH01161936A (en) * 1987-11-19 1989-06-26 American Teleph & Telegr Co <Att> Clock recovery apparatus using digital pll
JPH01264828A (en) * 1988-04-18 1989-10-23 Toyobo Co Ltd Biaxially oriented polyester film
JPH057925U (en) * 1991-07-12 1993-02-02 株式会社クボタ Water cooling system for forced circulation type water cooling engine

Similar Documents

Publication Publication Date Title
JPS5619263A (en) Waveform shaping circuit
JPS5435666A (en) Timing extraction system
EP0005127A3 (en) Improvement in systems of frequency translation of frequency-modulated signals
JPS5535545A (en) Digital phase synchronous circuit
JPS5431260A (en) Digital control phase synchronizing device
ES8106643A1 (en) Synchronizing an oscillator from a television signal
JPS5413734A (en) Synchronizing signal generator
GB2002186A (en) Frequency synchronization
JPS54141507A (en) Phase synchronism circuit
JPS6412691A (en) Video signal sampling circuit
JPS54124662A (en) Digital phase synchronizing loop
GB1520290A (en) Phase acquisition
JPS52106229A (en) Carrier wave signal formation circuit containing line offset
JPS57170688A (en) Jitter compensation circuit
JPS5754451A (en) Phase locked loop circuit for digital communication
JPS55146064A (en) Transmission beam former
JPS5520070A (en) Clock pulse generation circuit for picture broadcast receiver
JPS5216121A (en) Phase synchronizing system of multi subsystem
JPS5793723A (en) Phase alteration system
JPS5748842A (en) Frame synchronizing circuit
JPS5469321A (en) Vertical synchronizing equipment
JPS54151313A (en) Synchronizing timing generation circuit for reception bit
JPS5393721A (en) Frame synchronous circuit
JPS53110875A (en) Rapid feed signal generating circuit of digital clocks
GB800660A (en) Pulse communication system