JPS56159891A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPS56159891A JPS56159891A JP6306280A JP6306280A JPS56159891A JP S56159891 A JPS56159891 A JP S56159891A JP 6306280 A JP6306280 A JP 6306280A JP 6306280 A JP6306280 A JP 6306280A JP S56159891 A JPS56159891 A JP S56159891A
- Authority
- JP
- Japan
- Prior art keywords
- mode
- stand
- generator
- self
- active mode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
Abstract
PURPOSE:To reduce the current in the stand-by mode without deterlorating the characteristic in the active mode by changing the self-bias voltage based on the active mode and stand-by mode. CONSTITUTION:When a chip enable signal CE supplied to an input terminal 2-1 indicates the active mode, only a self-subbias generator 2-2 is operated and bias voltage VB outputted to an output terminal 2-5 becomes approximately -2.5V. The voltage VB is supplied to terminals 3-1-3-3 of an inverter circuit, causing a transistor TR T6 to be conductive and an input signal at an input terminal 3-4 is inverted to appear at an output terminal 3-6. When the signal CE then changes to the stand-by mode, only a self-subbias generator 2-4 is operated and the voltage VB becomes -5V. As the result, TR T6 is completely out off and power consumption is reduced. Further, since oscillating frequency also may well to reduce to 1/10-1/100, the power consumption of the generator 2-4 can also be 1/10-1/100.
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6306280A JPS56159891A (en) | 1980-05-13 | 1980-05-13 | Semiconductor integrated circuit device |
US06/260,994 US4460835A (en) | 1980-05-13 | 1981-05-06 | Semiconductor integrated circuit device with low power consumption in a standby mode using an on-chip substrate bias generator |
DE8181103606T DE3162416D1 (en) | 1980-05-13 | 1981-05-11 | Semiconductor integrated circuit device |
EP81103606A EP0039946B1 (en) | 1980-05-13 | 1981-05-11 | Semiconductor integrated circuit device |
CA000377457A CA1185665A (en) | 1980-05-13 | 1981-05-13 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6306280A JPS56159891A (en) | 1980-05-13 | 1980-05-13 | Semiconductor integrated circuit device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS56159891A true JPS56159891A (en) | 1981-12-09 |
JPS6213759B2 JPS6213759B2 (en) | 1987-03-28 |
Family
ID=13218469
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6306280A Granted JPS56159891A (en) | 1980-05-13 | 1980-05-13 | Semiconductor integrated circuit device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56159891A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH076583A (en) * | 1993-12-03 | 1995-01-10 | Hitachi Ltd | Semiconductor device |
JP2011254305A (en) * | 2010-06-02 | 2011-12-15 | Asahi Kasei Electronics Co Ltd | Clock negative booster circuit |
-
1980
- 1980-05-13 JP JP6306280A patent/JPS56159891A/en active Granted
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH076583A (en) * | 1993-12-03 | 1995-01-10 | Hitachi Ltd | Semiconductor device |
JP2011254305A (en) * | 2010-06-02 | 2011-12-15 | Asahi Kasei Electronics Co Ltd | Clock negative booster circuit |
Also Published As
Publication number | Publication date |
---|---|
JPS6213759B2 (en) | 1987-03-28 |
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