JPS56157153A - Data repeating device - Google Patents

Data repeating device

Info

Publication number
JPS56157153A
JPS56157153A JP6019980A JP6019980A JPS56157153A JP S56157153 A JPS56157153 A JP S56157153A JP 6019980 A JP6019980 A JP 6019980A JP 6019980 A JP6019980 A JP 6019980A JP S56157153 A JPS56157153 A JP S56157153A
Authority
JP
Japan
Prior art keywords
signal
data
terminal device
integrator
supplied
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6019980A
Other languages
Japanese (ja)
Inventor
Toshihiko Ohori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Priority to JP6019980A priority Critical patent/JPS56157153A/en
Publication of JPS56157153A publication Critical patent/JPS56157153A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L5/00—Arrangements affording multiple use of the transmission path
    • H04L5/14—Two-way operation using the same type of signal, i.e. duplex
    • H04L5/16—Half-duplex systems; Simplex/duplex switching; Transmission of break signals non-automatically inverting the direction of transmission

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Bidirectional Digital Transmission (AREA)
  • Dc Digital Transmission (AREA)

Abstract

PURPOSE:To facilitate a synchronism for the data of a terminal device, by installing an integral network at the two-way communication line of a semidouble communication system and thus performing a control of the output signal and an inhibition of the signal supplied from the other side through the said integral network. CONSTITUTION:A bit synchronism is secured at a terminal device when the data is transmitted to the terminal device from the center side, and thus a clock signal of idling is transmitted. When the signal is supplied to a data repeating device 10, the input signal is amplified by a line receiver 21a. The output signal of this amplification is supplied to an integrator 24a via an AND circuit 22a as well as to a line driver. The integrator 24a functions as a delaying circuit and thus delivers no clock signal while it functions as a delaying circuit but delivers the data only. At the same time, the integrator 24a sets the line driver under a high output impedance state during a delaying action and amplifies only the signal delivered from the center side to transmit it to the terminal device.
JP6019980A 1980-05-07 1980-05-07 Data repeating device Pending JPS56157153A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6019980A JPS56157153A (en) 1980-05-07 1980-05-07 Data repeating device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6019980A JPS56157153A (en) 1980-05-07 1980-05-07 Data repeating device

Publications (1)

Publication Number Publication Date
JPS56157153A true JPS56157153A (en) 1981-12-04

Family

ID=13135237

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6019980A Pending JPS56157153A (en) 1980-05-07 1980-05-07 Data repeating device

Country Status (1)

Country Link
JP (1) JPS56157153A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59198050A (en) * 1983-04-25 1984-11-09 Fuji Electric Corp Res & Dev Ltd Serial data reading circuit
JPS6014547A (en) * 1983-07-05 1985-01-25 Nec Corp Extension circuit of bidirectional signal line
JPS6113722A (en) * 1984-06-29 1986-01-22 Fuji Electric Co Ltd Signal transmitter device
JPS62193430A (en) * 1986-02-20 1987-08-25 Aihon Kk Regenerative repeater
JPS6374237A (en) * 1986-09-17 1988-04-04 Rinnai Corp Signal amplifier for semi-duplex communication equipment
JPS63123241A (en) * 1986-11-13 1988-05-27 Mitsubishi Electric Corp Relay communication equipment
JPH01103337A (en) * 1987-10-16 1989-04-20 Fujitsu Ltd Monitoring equipment

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59198050A (en) * 1983-04-25 1984-11-09 Fuji Electric Corp Res & Dev Ltd Serial data reading circuit
JPH0147065B2 (en) * 1983-04-25 1989-10-12 Fuji Denki Sogo Kenkyusho Kk
JPS6014547A (en) * 1983-07-05 1985-01-25 Nec Corp Extension circuit of bidirectional signal line
JPH035703B2 (en) * 1983-07-05 1991-01-28 Nippon Electric Co
JPS6113722A (en) * 1984-06-29 1986-01-22 Fuji Electric Co Ltd Signal transmitter device
JPS62193430A (en) * 1986-02-20 1987-08-25 Aihon Kk Regenerative repeater
JPS6374237A (en) * 1986-09-17 1988-04-04 Rinnai Corp Signal amplifier for semi-duplex communication equipment
JPS63123241A (en) * 1986-11-13 1988-05-27 Mitsubishi Electric Corp Relay communication equipment
JPH01103337A (en) * 1987-10-16 1989-04-20 Fujitsu Ltd Monitoring equipment

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