JPS56156992A - Driving circuit for semiconductor storage device - Google Patents

Driving circuit for semiconductor storage device

Info

Publication number
JPS56156992A
JPS56156992A JP6155580A JP6155580A JPS56156992A JP S56156992 A JPS56156992 A JP S56156992A JP 6155580 A JP6155580 A JP 6155580A JP 6155580 A JP6155580 A JP 6155580A JP S56156992 A JPS56156992 A JP S56156992A
Authority
JP
Japan
Prior art keywords
voltage
terminal
power source
semiconductor storage
storage device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6155580A
Other languages
Japanese (ja)
Other versions
JPS6011396B2 (en
Inventor
Masao Furuta
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP55061555A priority Critical patent/JPS6011396B2/en
Publication of JPS56156992A publication Critical patent/JPS56156992A/en
Publication of JPS6011396B2 publication Critical patent/JPS6011396B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/22—Safety or protection circuits preventing unauthorised or accidental access to memory cells
    • G11C16/225—Preventing erasure, programming or reading when power supply voltages are outside the required ranges

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Static Random-Access Memory (AREA)
  • Read Only Memory (AREA)

Abstract

PURPOSE:To prevent the change in the storage state of an electrically write enable nonvoltage memory at the closing of a power source or the like by adding a priority circuit and inhibiting the other power source supply until the voltage for driving logical circuits is stabilized. CONSTITUTION:When the divided voltage from the 1st power source terminal 3 divided by resistances 14, 15 is not applied and the voltage from the 2nd power source terminal 7 is being applied, the output of an inverter 16 falls to a low level, and the outputs of NAND circuits 17-19 rise to a high level, giving no influence upon a semiconductor storage device 1. The same holds true of the case when the voltage from the terminal 3 is applied to the inverter 16 and the voltage from the terminal 7 is not applied. On the other hand, the output of this inverter 16 for determining priority inverts to a high level only when a driving device 2 for controlling the semiconductor storage device is stabilized by the voltage from the terminal 3 and the voltage from the terminal 7 is applied, thereby enabling the rewriting of the device 1 through the device 2.
JP55061555A 1980-05-08 1980-05-08 Semiconductor storage device drive circuit Expired JPS6011396B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55061555A JPS6011396B2 (en) 1980-05-08 1980-05-08 Semiconductor storage device drive circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55061555A JPS6011396B2 (en) 1980-05-08 1980-05-08 Semiconductor storage device drive circuit

Publications (2)

Publication Number Publication Date
JPS56156992A true JPS56156992A (en) 1981-12-03
JPS6011396B2 JPS6011396B2 (en) 1985-03-25

Family

ID=13174468

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55061555A Expired JPS6011396B2 (en) 1980-05-08 1980-05-08 Semiconductor storage device drive circuit

Country Status (1)

Country Link
JP (1) JPS6011396B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6085498A (en) * 1983-10-18 1985-05-14 Toshiba Corp Semiconductor integrated circuit
FR2600809A1 (en) * 1986-06-24 1987-12-31 Eurotechnique Sa DEVICE FOR DETECTING THE OPERATION OF THE READING SYSTEM OF A MEMORY-CELL EPROM OR EEPROM
JPS63102096A (en) * 1986-09-30 1988-05-06 トムソン・コンポザン・ミリテール・エ・スパシオ Logical circuit type integrated circuit containing electrically programmable non- volatile memory
FR2640798A1 (en) * 1988-12-20 1990-06-22 Bull Cp8 DATA PROCESSING DEVICE COMPRISING A NON-VOLATILE MEMORY ELECTRICALLY DELETE AND REPROGRAMMABLE

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6085498A (en) * 1983-10-18 1985-05-14 Toshiba Corp Semiconductor integrated circuit
FR2600809A1 (en) * 1986-06-24 1987-12-31 Eurotechnique Sa DEVICE FOR DETECTING THE OPERATION OF THE READING SYSTEM OF A MEMORY-CELL EPROM OR EEPROM
US4908799A (en) * 1986-06-24 1990-03-13 Thomson Composants Militaires Et Spatiaux Device to detect the functioning of the read system of an EPROM or EEPROM memory cell
JPS63102096A (en) * 1986-09-30 1988-05-06 トムソン・コンポザン・ミリテール・エ・スパシオ Logical circuit type integrated circuit containing electrically programmable non- volatile memory
FR2640798A1 (en) * 1988-12-20 1990-06-22 Bull Cp8 DATA PROCESSING DEVICE COMPRISING A NON-VOLATILE MEMORY ELECTRICALLY DELETE AND REPROGRAMMABLE

Also Published As

Publication number Publication date
JPS6011396B2 (en) 1985-03-25

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