JPS5613853A - Band variable type timing reproducing circuit - Google Patents
Band variable type timing reproducing circuitInfo
- Publication number
- JPS5613853A JPS5613853A JP8960279A JP8960279A JPS5613853A JP S5613853 A JPS5613853 A JP S5613853A JP 8960279 A JP8960279 A JP 8960279A JP 8960279 A JP8960279 A JP 8960279A JP S5613853 A JPS5613853 A JP S5613853A
- Authority
- JP
- Japan
- Prior art keywords
- pll
- output
- lead
- agc
- mixer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000001360 synchronised effect Effects 0.000 abstract 2
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
Landscapes
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
PURPOSE:To secure a continuous change for the equivalent noise band width of the PLL, by adding the AGC in front of the PLL circuit and then setting the band of the AGC substantially equal to the lead-in frequency range of the PLL. CONSTITUTION:AGC12 is added in front of PLL circuit 11. And now if no synchronism is secured for the PLL loop, the output of mixer 7 for synchronous component becomes 0. At the same time, the output of adder 9 turns to output voltage -Vref of reference voltage generator 10, and amplifier 2 has the gain close to the maximum gain. If the synchronism of PLL11 is secured under these conditions, mixer 7 produces the output equal to the amplitude of the arrival signal. And the output of mixer 7 becomes equal to voltage Vref, and the gain of amplifier 2 is set so that the AGC control voltage may be 0. Then the band of AGC12 is set equal substantially to the lead-in frequency range of PLL11, and the AGC is actuated after lead-in of the PLL. Then the input signal to the PLL is reduced to secure the synchronous lead-in in a high speed and in a wide frequency range. Thus the equivalent noise band width can be changed continuously.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8960279A JPS5613853A (en) | 1979-07-13 | 1979-07-13 | Band variable type timing reproducing circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8960279A JPS5613853A (en) | 1979-07-13 | 1979-07-13 | Band variable type timing reproducing circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5613853A true JPS5613853A (en) | 1981-02-10 |
Family
ID=13975303
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8960279A Pending JPS5613853A (en) | 1979-07-13 | 1979-07-13 | Band variable type timing reproducing circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5613853A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0221738A (en) * | 1988-05-12 | 1990-01-24 | Digital Equip Corp <Dec> | Phase locking loop with graded band width |
WO2003056558A1 (en) * | 2001-12-26 | 2003-07-10 | Matsushita Electric Industrial Co., Ltd. | Optical disc apparatus |
-
1979
- 1979-07-13 JP JP8960279A patent/JPS5613853A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0221738A (en) * | 1988-05-12 | 1990-01-24 | Digital Equip Corp <Dec> | Phase locking loop with graded band width |
WO2003056558A1 (en) * | 2001-12-26 | 2003-07-10 | Matsushita Electric Industrial Co., Ltd. | Optical disc apparatus |
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