JPS5612583A - Programable timer - Google Patents

Programable timer

Info

Publication number
JPS5612583A
JPS5612583A JP8875679A JP8875679A JPS5612583A JP S5612583 A JPS5612583 A JP S5612583A JP 8875679 A JP8875679 A JP 8875679A JP 8875679 A JP8875679 A JP 8875679A JP S5612583 A JPS5612583 A JP S5612583A
Authority
JP
Japan
Prior art keywords
time
timer output
detected
circuit
counter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8875679A
Other languages
Japanese (ja)
Inventor
Yushi Sano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP8875679A priority Critical patent/JPS5612583A/en
Publication of JPS5612583A publication Critical patent/JPS5612583A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To simplify the time setting operation by performing the setting of the holding time until the timer output becomes off by detecting that the timer output becomes zero, and carrying out a sleeping mode operation using an off-time counter.
CONSTITUTION: When an on-time is detected by a coincidence detecting circuit 48, an off-time counter 52 starts count-down by a clock signal from a count-down circuit 43. When "0" is detected 54, a timer output control circuit 50 is controlled, and set information of an off-time memory 53 is automatially set at the off time counter 52, thus stand-by state being assumed. When a sleeping mode operation is started, the timer output control circuit 50 forcibly leads out an on-output by a signal from a mode selecting circuit 41. Furthermore, the off-counter 52 starts down counting and when "0" is detected 54, the timer output is turned off.
COPYRIGHT: (C)1981,JPO&Japio
JP8875679A 1979-07-13 1979-07-13 Programable timer Pending JPS5612583A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8875679A JPS5612583A (en) 1979-07-13 1979-07-13 Programable timer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8875679A JPS5612583A (en) 1979-07-13 1979-07-13 Programable timer

Publications (1)

Publication Number Publication Date
JPS5612583A true JPS5612583A (en) 1981-02-06

Family

ID=13951724

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8875679A Pending JPS5612583A (en) 1979-07-13 1979-07-13 Programable timer

Country Status (1)

Country Link
JP (1) JPS5612583A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60218981A (en) * 1984-03-05 1985-11-01 アールシーエー　トムソン　ライセンシング　コーポレーシヨン Television system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60218981A (en) * 1984-03-05 1985-11-01 アールシーエー　トムソン　ライセンシング　コーポレーシヨン Television system
JPH0566788B2 (en) * 1984-03-05 1993-09-22 Rca Thomson Licensing Corp

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