JPS5612550A - Control device for peak process time - Google Patents

Control device for peak process time

Info

Publication number
JPS5612550A
JPS5612550A JP8825879A JP8825879A JPS5612550A JP S5612550 A JPS5612550 A JP S5612550A JP 8825879 A JP8825879 A JP 8825879A JP 8825879 A JP8825879 A JP 8825879A JP S5612550 A JPS5612550 A JP S5612550A
Authority
JP
Japan
Prior art keywords
circuit
output
fed
peak
compensating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8825879A
Other languages
Japanese (ja)
Inventor
Tadashi Nishino
Makoto Kogure
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP8825879A priority Critical patent/JPS5612550A/en
Publication of JPS5612550A publication Critical patent/JPS5612550A/en
Pending legal-status Critical Current

Links

Landscapes

  • Measurement Of Current Or Voltage (AREA)
  • Treatment Of Liquids With Adsorbents In General (AREA)

Abstract

PURPOSE: To integrate the area of chromatograph exactly by compensating a component selection starting time and a termination time separately according to the shift of the peak.
CONSTITUTION: An input signal of the chromatograph is fed to the amplifier 1 and the counter 2. The output of the amplifier 1 is provided to the comparators 4W6 together with the slope sensitivity set values S, T, E of the peak. The counter 2 is connected to the memories 7W9. Outputs of both comparators 12, 13 are obtained as a decision value H1 through the ANd circuit 14. The output of the AND circuit 14 is fed to the AND circuit 16 together with the output of the arithmetic circuit 15, and a decision value H2 is obtained. The output of the AND circuit 16 is provided to the compensating circuit 17, to which the output of the arithmetic circuit 15 is also fed. The stored values of the memories 10, 11 are updated by the output of the compensating circuit 17.
COPYRIGHT: (C)1981,JPO&Japio
JP8825879A 1979-07-13 1979-07-13 Control device for peak process time Pending JPS5612550A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8825879A JPS5612550A (en) 1979-07-13 1979-07-13 Control device for peak process time

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8825879A JPS5612550A (en) 1979-07-13 1979-07-13 Control device for peak process time

Publications (1)

Publication Number Publication Date
JPS5612550A true JPS5612550A (en) 1981-02-06

Family

ID=13937842

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8825879A Pending JPS5612550A (en) 1979-07-13 1979-07-13 Control device for peak process time

Country Status (1)

Country Link
JP (1) JPS5612550A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01112458U (en) * 1988-01-23 1989-07-28

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01112458U (en) * 1988-01-23 1989-07-28

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