JPS56125133A - Scramble system - Google Patents
Scramble systemInfo
- Publication number
- JPS56125133A JPS56125133A JP2834280A JP2834280A JPS56125133A JP S56125133 A JPS56125133 A JP S56125133A JP 2834280 A JP2834280 A JP 2834280A JP 2834280 A JP2834280 A JP 2834280A JP S56125133 A JPS56125133 A JP S56125133A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- fed
- signal
- pulse train
- virtual random
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03828—Arrangements for spectral shaping; Arrangements for providing signals with specified spectral properties
- H04L25/03866—Arrangements for spectral shaping; Arrangements for providing signals with specified spectral properties using scrambling
Abstract
PURPOSE:To enable to surely detect the produced location of special signal at the reception side, by the transmission with the code of different code system in which the special signal such as frame synchronism signal and data signal can independently be identified. CONSTITUTION:A shift register 12 and an exclusive logical sum gate 11 constitute a virtual random pattern generating circuit, and the virtual random pattern train is fed to an exclusive OR gate 14 via an inhibition gate 13 when the output signal (a) of the timing generating circuit 16 is ''0'', that is, other than the produced location of the frame synchronizing signal, and the input pulse train S7 from the input pulse train generating circuit 15 is scrambled with the virtual random pulse train and fed to the code conversion circuit 17. If (a) is ''1'', the inhibition gate 13 is off, and the virtual random pulse train is not fed to the exclusive OR gate 14 but fed to the circuit 17.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2834280A JPS56125133A (en) | 1980-03-06 | 1980-03-06 | Scramble system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2834280A JPS56125133A (en) | 1980-03-06 | 1980-03-06 | Scramble system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS56125133A true JPS56125133A (en) | 1981-10-01 |
Family
ID=12245916
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2834280A Pending JPS56125133A (en) | 1980-03-06 | 1980-03-06 | Scramble system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56125133A (en) |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4843209A (en) * | 1971-10-01 | 1973-06-22 | ||
JPS5366318A (en) * | 1976-11-26 | 1978-06-13 | Fujitsu Ltd | Scramble system |
JPS5412207A (en) * | 1977-06-17 | 1979-01-29 | Nec Corp | Signal transmission system |
JPS5412203A (en) * | 1976-11-26 | 1979-01-29 | Paradyne Corp | Digital modem |
-
1980
- 1980-03-06 JP JP2834280A patent/JPS56125133A/en active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4843209A (en) * | 1971-10-01 | 1973-06-22 | ||
JPS5366318A (en) * | 1976-11-26 | 1978-06-13 | Fujitsu Ltd | Scramble system |
JPS5412203A (en) * | 1976-11-26 | 1979-01-29 | Paradyne Corp | Digital modem |
JPS5412207A (en) * | 1977-06-17 | 1979-01-29 | Nec Corp | Signal transmission system |
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