JPS56124961A - Information processing equipment - Google Patents

Information processing equipment

Info

Publication number
JPS56124961A
JPS56124961A JP2655180A JP2655180A JPS56124961A JP S56124961 A JPS56124961 A JP S56124961A JP 2655180 A JP2655180 A JP 2655180A JP 2655180 A JP2655180 A JP 2655180A JP S56124961 A JPS56124961 A JP S56124961A
Authority
JP
Japan
Prior art keywords
buffer
disc
data
range
stored
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2655180A
Other languages
Japanese (ja)
Inventor
Hiroo Miyadera
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP2655180A priority Critical patent/JPS56124961A/en
Publication of JPS56124961A publication Critical patent/JPS56124961A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0864Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing

Abstract

PURPOSE:To elevate the bit rate of a buffer by designating an address range of a data on the disc equipment, and allowing to use the buffer to only a data in said range. CONSTITUTION:When a request address is in the range disignated by the register 2 containing the upper limit value of address and the register 3 containing the lower limit value, and it is registered in the register group (BAA)8, a data is read out from the disk buffer. If it is out of the range, a regular disc access operation is executed by an output signal 32 of the inverter 7. And, even if it is out of the range, in case when a control signal 12 showing that it is not stored in the disc buffer is provided as an output of the AND circuit 11, a data is derived from the disc equipment by the signal 12, and after that, a block containing said data is stored in the disc buffer. Also, the contents of the BAA8 are stored, as well. Furthermore, the contents of the BAA are also updated. In this way, only an effective file of the disc buffer can be selected, and an efficient processing is made.
JP2655180A 1980-03-05 1980-03-05 Information processing equipment Pending JPS56124961A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2655180A JPS56124961A (en) 1980-03-05 1980-03-05 Information processing equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2655180A JPS56124961A (en) 1980-03-05 1980-03-05 Information processing equipment

Publications (1)

Publication Number Publication Date
JPS56124961A true JPS56124961A (en) 1981-09-30

Family

ID=12196649

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2655180A Pending JPS56124961A (en) 1980-03-05 1980-03-05 Information processing equipment

Country Status (1)

Country Link
JP (1) JPS56124961A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5960552A (en) * 1982-09-27 1984-04-06 インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション Peripheral data memory system
JPS6345655A (en) * 1986-08-12 1988-02-26 Fujitsu Ltd Control system for cache memory
JPH04330540A (en) * 1991-05-02 1992-11-18 Mitsubishi Electric Corp Microcomputer control system
JPH06295263A (en) * 1993-04-08 1994-10-21 Mitsubishi Electric Corp Memory system

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55154648A (en) * 1979-05-22 1980-12-02 Nec Corp Disc cash control system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55154648A (en) * 1979-05-22 1980-12-02 Nec Corp Disc cash control system

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5960552A (en) * 1982-09-27 1984-04-06 インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション Peripheral data memory system
JPS6345655A (en) * 1986-08-12 1988-02-26 Fujitsu Ltd Control system for cache memory
JPH04330540A (en) * 1991-05-02 1992-11-18 Mitsubishi Electric Corp Microcomputer control system
JPH06295263A (en) * 1993-04-08 1994-10-21 Mitsubishi Electric Corp Memory system

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