JPS56110127A - Data transfer control system - Google Patents

Data transfer control system

Info

Publication number
JPS56110127A
JPS56110127A JP1244980A JP1244980A JPS56110127A JP S56110127 A JPS56110127 A JP S56110127A JP 1244980 A JP1244980 A JP 1244980A JP 1244980 A JP1244980 A JP 1244980A JP S56110127 A JPS56110127 A JP S56110127A
Authority
JP
Japan
Prior art keywords
data transfer
memory
module
controller
controls
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1244980A
Other languages
Japanese (ja)
Inventor
Hiroto Katsumata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP1244980A priority Critical patent/JPS56110127A/en
Publication of JPS56110127A publication Critical patent/JPS56110127A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Abstract

PURPOSE:To simplify the system and also make it inexpensive, by transferring a data between the high-rank system or the input/output device controller, and the memory, by use of the data transfer module. CONSTITUTION:In case when a command which has been sent as an interface signal 72 from the high-rank system is of a write transfer to the I/O connected to the input/output device controller 41, the data transfer module 51 controls a data transfer from the system interface unit 3 to the local memory 2. When the data has been stored in the memory 2, the data transfer module 62 is started. The module 52 controls a data transfer from the memory 2 to the controller 41. Subsequently, in case when a command which has been sent as a signal 72 from the high-rank system is of a read transfer to the I/O connected to the controller 41, the module 52 controls a data transfer from the controller 41 to the memory 2. Subsequently, the module 51 controls a transfer from the memory 2 to the controller 41.
JP1244980A 1980-02-06 1980-02-06 Data transfer control system Pending JPS56110127A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1244980A JPS56110127A (en) 1980-02-06 1980-02-06 Data transfer control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1244980A JPS56110127A (en) 1980-02-06 1980-02-06 Data transfer control system

Publications (1)

Publication Number Publication Date
JPS56110127A true JPS56110127A (en) 1981-09-01

Family

ID=11805640

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1244980A Pending JPS56110127A (en) 1980-02-06 1980-02-06 Data transfer control system

Country Status (1)

Country Link
JP (1) JPS56110127A (en)

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