JPS56101259A - Prevention system of common memory competition - Google Patents

Prevention system of common memory competition

Info

Publication number
JPS56101259A
JPS56101259A JP355580A JP355580A JPS56101259A JP S56101259 A JPS56101259 A JP S56101259A JP 355580 A JP355580 A JP 355580A JP 355580 A JP355580 A JP 355580A JP S56101259 A JPS56101259 A JP S56101259A
Authority
JP
Japan
Prior art keywords
common memory
competition
common
control section
occupied
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP355580A
Other languages
Japanese (ja)
Inventor
Setsuo Minamide
Yutaka Kubo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP355580A priority Critical patent/JPS56101259A/en
Publication of JPS56101259A publication Critical patent/JPS56101259A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)

Abstract

PURPOSE:To prevent the access competition for common area without using the communication means between computers, by providing the interlock register corresponding to the competitive area at the common memory unit side. CONSTITUTION:A plurality of computers 1, 2 are connected to a common memory 3 via a memory access control section 4. The common memory unit 5 has the interlock register control section 6 and the occupied time monitor section 7 in addition to the said memory 3 and the control section 4. This occupied time monitor section 7 monitors the occupied time of interlock and stops the occupied computer acccompanied with the timeout of the monitoring time, allowing to prevent the competition of the common memory.
JP355580A 1980-01-18 1980-01-18 Prevention system of common memory competition Pending JPS56101259A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP355580A JPS56101259A (en) 1980-01-18 1980-01-18 Prevention system of common memory competition

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP355580A JPS56101259A (en) 1980-01-18 1980-01-18 Prevention system of common memory competition

Publications (1)

Publication Number Publication Date
JPS56101259A true JPS56101259A (en) 1981-08-13

Family

ID=11560665

Family Applications (1)

Application Number Title Priority Date Filing Date
JP355580A Pending JPS56101259A (en) 1980-01-18 1980-01-18 Prevention system of common memory competition

Country Status (1)

Country Link
JP (1) JPS56101259A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6079462A (en) * 1983-07-21 1985-05-07 バロ−ス・コ−ポレ−シヨン Controller for controlling access to multiple records
JPH02113321A (en) * 1988-10-24 1990-04-25 Nec Corp Control system for shared disk device
JPH02230361A (en) * 1989-03-02 1990-09-12 Nec Corp Lock sequence malfeasance detecting mechanism for information processor
JPH05282166A (en) * 1992-01-17 1993-10-29 Internatl Business Mach Corp <Ibm> Device for restoring dropout buffer in data processing system
JPWO2007138995A1 (en) * 2006-05-26 2009-10-08 Nok株式会社 Dust cover fixing bracket

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6079462A (en) * 1983-07-21 1985-05-07 バロ−ス・コ−ポレ−シヨン Controller for controlling access to multiple records
JPH02113321A (en) * 1988-10-24 1990-04-25 Nec Corp Control system for shared disk device
JPH02230361A (en) * 1989-03-02 1990-09-12 Nec Corp Lock sequence malfeasance detecting mechanism for information processor
JPH05282166A (en) * 1992-01-17 1993-10-29 Internatl Business Mach Corp <Ibm> Device for restoring dropout buffer in data processing system
JPWO2007138995A1 (en) * 2006-05-26 2009-10-08 Nok株式会社 Dust cover fixing bracket

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