JPS5592054A - Unique word detection circuit - Google Patents

Unique word detection circuit

Info

Publication number
JPS5592054A
JPS5592054A JP16512678A JP16512678A JPS5592054A JP S5592054 A JPS5592054 A JP S5592054A JP 16512678 A JP16512678 A JP 16512678A JP 16512678 A JP16512678 A JP 16512678A JP S5592054 A JPS5592054 A JP S5592054A
Authority
JP
Japan
Prior art keywords
unique word
disagreement
bits
pattern
rom12
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16512678A
Other languages
Japanese (ja)
Inventor
Yukio Miyazaki
Shigeru Hamada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16512678A priority Critical patent/JPS5592054A/en
Publication of JPS5592054A publication Critical patent/JPS5592054A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04JMULTIPLEX COMMUNICATION
    • H04J3/00Time-division multiplex systems
    • H04J3/02Details
    • H04J3/06Synchronising arrangements
    • H04J3/0602Systems characterised by the synchronising information used
    • H04J3/0605Special codes used as synchronising signal
    • H04J3/0608Detectors therefor, e.g. correlators, state machines

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To make it possible to reduce the amount of hardware by detecting disagreement between an input pattern and a unique word pattern with bit correspondence and by deciding whether the number of disagreement bits is below the number of allowable error bits or not. CONSTITUTION:Input data is inputted to series-parallel conversion shift register SPSR11 serially, and the parallel output addresses P-ROM12 directly, and disagreement between the input pattern and a unique word pattern is detected with bit correspondence. The output of P-ROM12 is applied to a decision circuit to decide whether the number of disagreement bits is below the number of allowable error bits or not, thereby detecting the unique word. As a result, digital addition without trouble on precision can be performed, and the amount of hardware can be reduced.
JP16512678A 1978-12-29 1978-12-29 Unique word detection circuit Pending JPS5592054A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16512678A JPS5592054A (en) 1978-12-29 1978-12-29 Unique word detection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16512678A JPS5592054A (en) 1978-12-29 1978-12-29 Unique word detection circuit

Publications (1)

Publication Number Publication Date
JPS5592054A true JPS5592054A (en) 1980-07-12

Family

ID=15806397

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16512678A Pending JPS5592054A (en) 1978-12-29 1978-12-29 Unique word detection circuit

Country Status (1)

Country Link
JP (1) JPS5592054A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60247344A (en) * 1984-05-23 1985-12-07 Hitachi Ltd Synchronizing signal detecting circuit
FR2568073A1 (en) * 1984-07-20 1986-01-24 Telecommunications Sa DEVICE FOR LOSSING AND RECOVERING FRAME LOCK FOR DIGITAL SIGNAL.
JPS62224138A (en) * 1986-03-26 1987-10-02 Kenwood Corp Frame synchronizing pattern correlation detection circuit
JPH03184439A (en) * 1989-12-13 1991-08-12 Nec Corp Unique word detecting system
WO1997008858A1 (en) * 1995-08-23 1997-03-06 Gpt Limited Time multiplexing/demultiplexing method

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60247344A (en) * 1984-05-23 1985-12-07 Hitachi Ltd Synchronizing signal detecting circuit
FR2568073A1 (en) * 1984-07-20 1986-01-24 Telecommunications Sa DEVICE FOR LOSSING AND RECOVERING FRAME LOCK FOR DIGITAL SIGNAL.
JPS62224138A (en) * 1986-03-26 1987-10-02 Kenwood Corp Frame synchronizing pattern correlation detection circuit
JPH03184439A (en) * 1989-12-13 1991-08-12 Nec Corp Unique word detecting system
WO1997008858A1 (en) * 1995-08-23 1997-03-06 Gpt Limited Time multiplexing/demultiplexing method

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