JPS5587470A - Substrate bias circuit of mos integrated circuit - Google Patents

Substrate bias circuit of mos integrated circuit

Info

Publication number
JPS5587470A
JPS5587470A JP16043178A JP16043178A JPS5587470A JP S5587470 A JPS5587470 A JP S5587470A JP 16043178 A JP16043178 A JP 16043178A JP 16043178 A JP16043178 A JP 16043178A JP S5587470 A JPS5587470 A JP S5587470A
Authority
JP
Japan
Prior art keywords
output
vth
potential
terminal
type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16043178A
Other languages
Japanese (ja)
Inventor
Akiyoshi Kanuma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP16043178A priority Critical patent/JPS5587470A/en
Publication of JPS5587470A publication Critical patent/JPS5587470A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/205—Substrate bias-voltage generators

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To vary the substrate bias according to the output voltage of the inverter by controlling the level of clamp potential through selective connection to the feedback path with application of a bootstrap type feedback to FET under the load of an E (enhancement) type MOS inverter. CONSTITUTION:The output of a generator 1 drives an E-type inverter 2 employing a MOSFET Q7/Q8. When the output is VH, a MOSFET Q11 is turned on, and D (depletion) type MOSFET Q10 is charged so that the potential of the contact e reaches -VH at OV. Therefore, if the threshold of the E-type MOSFET is VTH, the output VTH-VH develops at the terminal f. When the gate input of the D-type MOSFET Q9 is OV while the output terminal c is at OV, the potential of a contact d on the D-type MOSFET Q13 (capacity) reaches 2VDD-VTH. Thus, the potential VTH-VDD develops at the terminal f. When a high level input is applied to the gate a, the FET Q9 is turned on and the contact d is clamped at a potential VDD. Only the output VDD-VTH develops at the output terminal, leading the output of the terminal f to be 2VTH-VDD. In this manner, the power consumption and the working speed can be switched by changing the bias of the substrate.
JP16043178A 1978-12-25 1978-12-25 Substrate bias circuit of mos integrated circuit Pending JPS5587470A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16043178A JPS5587470A (en) 1978-12-25 1978-12-25 Substrate bias circuit of mos integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16043178A JPS5587470A (en) 1978-12-25 1978-12-25 Substrate bias circuit of mos integrated circuit

Publications (1)

Publication Number Publication Date
JPS5587470A true JPS5587470A (en) 1980-07-02

Family

ID=15714778

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16043178A Pending JPS5587470A (en) 1978-12-25 1978-12-25 Substrate bias circuit of mos integrated circuit

Country Status (1)

Country Link
JP (1) JPS5587470A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57186351A (en) * 1981-05-12 1982-11-16 Fujitsu Ltd Semiconductor device
US4628214A (en) * 1985-05-22 1986-12-09 Sgs Semiconductor Corporation Back bias generator
US6097113A (en) * 1997-10-14 2000-08-01 Mitsubishi Denki Kabushiki Kaisha MOS integrated circuit device operating with low power consumption

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57186351A (en) * 1981-05-12 1982-11-16 Fujitsu Ltd Semiconductor device
JPH0318346B2 (en) * 1981-05-12 1991-03-12 Fujitsu Ltd
US4628214A (en) * 1985-05-22 1986-12-09 Sgs Semiconductor Corporation Back bias generator
US6097113A (en) * 1997-10-14 2000-08-01 Mitsubishi Denki Kabushiki Kaisha MOS integrated circuit device operating with low power consumption
US6333571B1 (en) 1997-10-14 2001-12-25 Mitsubishi Denki Kabushiki Kaisha MOS integrated circuit device operating with low power consumption

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