JPS5557106A - Automatic offset system for recorder - Google Patents

Automatic offset system for recorder

Info

Publication number
JPS5557106A
JPS5557106A JP12938078A JP12938078A JPS5557106A JP S5557106 A JPS5557106 A JP S5557106A JP 12938078 A JP12938078 A JP 12938078A JP 12938078 A JP12938078 A JP 12938078A JP S5557106 A JPS5557106 A JP S5557106A
Authority
JP
Japan
Prior art keywords
measured
age
converter
ein
instruments
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12938078A
Other languages
Japanese (ja)
Other versions
JPS5817408B2 (en
Inventor
Ryoji Gamo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP53129380A priority Critical patent/JPS5817408B2/en
Publication of JPS5557106A publication Critical patent/JPS5557106A/en
Publication of JPS5817408B2 publication Critical patent/JPS5817408B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Indication And Recording Devices For Special Purposes And Tariff Metering Devices (AREA)

Abstract

PURPOSE: To secure an accurate and quick recording for the characteristic change with age of the measured instruments by securing an automatic offset adjustment to subtract the absolute value output signal in case the characteristic change with age is measured for the measured instruments.
CONSTITUTION: With turning on of bias calibration switch 13 while measured signal eIN is supplied to comparator circuit 11 from the measured instrument, up-counter 15 is reset. And the counting is started from 0 with every input of clock signal CLK, and the count value is memorized and held. Accordingly, offset voltage ef of D/A converter 12 increases gradually. And the counting action is stopped when eIN< ef is secured, and the value of ef is held at converter 12. As a result, signal eIN and voltage ef of converter 12 are supplied to differential amplifier 19, and the absolute value output signal of the measured instruments is subtracted automatically to deliver voltage e0 showing the change with age.
COPYRIGHT: (C)1980,JPO&Japio
JP53129380A 1978-10-20 1978-10-20 Automatic offset method of recording device Expired JPS5817408B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53129380A JPS5817408B2 (en) 1978-10-20 1978-10-20 Automatic offset method of recording device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53129380A JPS5817408B2 (en) 1978-10-20 1978-10-20 Automatic offset method of recording device

Publications (2)

Publication Number Publication Date
JPS5557106A true JPS5557106A (en) 1980-04-26
JPS5817408B2 JPS5817408B2 (en) 1983-04-07

Family

ID=15008141

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53129380A Expired JPS5817408B2 (en) 1978-10-20 1978-10-20 Automatic offset method of recording device

Country Status (1)

Country Link
JP (1) JPS5817408B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62155317U (en) * 1986-03-26 1987-10-02
JPS6432116A (en) * 1987-07-29 1989-02-02 Hioki Electric Works Zero adjusting circuit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4974079A (en) * 1972-11-14 1974-07-17

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4974079A (en) * 1972-11-14 1974-07-17

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62155317U (en) * 1986-03-26 1987-10-02
JPS6432116A (en) * 1987-07-29 1989-02-02 Hioki Electric Works Zero adjusting circuit

Also Published As

Publication number Publication date
JPS5817408B2 (en) 1983-04-07

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