JPS5550790A - Signal processing device - Google Patents

Signal processing device

Info

Publication number
JPS5550790A
JPS5550790A JP12396978A JP12396978A JPS5550790A JP S5550790 A JPS5550790 A JP S5550790A JP 12396978 A JP12396978 A JP 12396978A JP 12396978 A JP12396978 A JP 12396978A JP S5550790 A JPS5550790 A JP S5550790A
Authority
JP
Japan
Prior art keywords
circuit
signal
output
multiplied
multiplying
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12396978A
Other languages
Japanese (ja)
Inventor
Tomio Ogawara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP12396978A priority Critical patent/JPS5550790A/en
Publication of JPS5550790A publication Critical patent/JPS5550790A/en
Pending legal-status Critical Current

Links

Landscapes

  • Picture Signal Circuits (AREA)
  • Television Systems (AREA)

Abstract

PURPOSE: To improve S/N at the same time of the processing by picturing the stationary object to be photographed, memorizong the signal by one field thereafter making the constant of the operating circuit variable.
CONSTITUTION: nth signal x(nT) of the sampling space of T is inputted from the terminal 13, and multiplied by K(n) in the multiplying circuit 14. The data in which the signal y(nT) from the signal output terminal 18 is sampled and delayed by the delay circuit 17 is multiplied by 1-K(n) in the multiplying circuit 15. The result thereof is added by the output from the mulplying circuit 14 in the adding circuit 16 to output. Accordingly, the coefficient K(n) of the multiplying circuit is changed, and then the most efficient S/N improvement can be carried out.
COPYRIGHT: (C)1980,JPO&Japio
JP12396978A 1978-10-06 1978-10-06 Signal processing device Pending JPS5550790A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12396978A JPS5550790A (en) 1978-10-06 1978-10-06 Signal processing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12396978A JPS5550790A (en) 1978-10-06 1978-10-06 Signal processing device

Publications (1)

Publication Number Publication Date
JPS5550790A true JPS5550790A (en) 1980-04-12

Family

ID=14873789

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12396978A Pending JPS5550790A (en) 1978-10-06 1978-10-06 Signal processing device

Country Status (1)

Country Link
JP (1) JPS5550790A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5966273A (en) * 1982-09-15 1984-04-14 ロ−ベルト・ボツシユ・ゲゼルシヤフト・ミツト・ベシユレンクテル・ハフツング Noise reducing device for television signal

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5966273A (en) * 1982-09-15 1984-04-14 ロ−ベルト・ボツシユ・ゲゼルシヤフト・ミツト・ベシユレンクテル・ハフツング Noise reducing device for television signal
JPH0574266B2 (en) * 1982-09-15 1993-10-18 Bosch Gmbh Robert

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