JPS5543660A - Microcomputer debug device - Google Patents

Microcomputer debug device

Info

Publication number
JPS5543660A
JPS5543660A JP11656978A JP11656978A JPS5543660A JP S5543660 A JPS5543660 A JP S5543660A JP 11656978 A JP11656978 A JP 11656978A JP 11656978 A JP11656978 A JP 11656978A JP S5543660 A JPS5543660 A JP S5543660A
Authority
JP
Japan
Prior art keywords
signal
generator
given
memory
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11656978A
Other languages
Japanese (ja)
Inventor
Shigenori Kawamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Denshi KK
Original Assignee
Hitachi Denshi KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Denshi KK filed Critical Hitachi Denshi KK
Priority to JP11656978A priority Critical patent/JPS5543660A/en
Publication of JPS5543660A publication Critical patent/JPS5543660A/en
Pending legal-status Critical Current

Links

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  • Debugging And Monitoring (AREA)

Abstract

PURPOSE: To always ensure the supervision for the contents of the memory by compounding the output of the hexadecimal digit generator and the output of the synchronous signal generator through the video signal generator and then sending the composite output to the CRT.
CONSTITUTION: Memory 4 is controlled by the read/write signal sent from the microcomputer, the address signal and the data signal each. Switch circuit 1 operates on the chip selection signal given from the microcomputer to control the read/ write for the memory. Here address signal generator 6 synchronized with the signal given from synchronous signal generator 5 to generate the address signal and is actuated by the chip selection signal given from the computer to switch the address signals given from the computer and generator 6 to apply them to memory 4. Then the output of hexadecimal generator 9 is compounded with the synchronous signal given from generator 5 through video signal generator 10 to be sent to the CRT in the form of the video signal. Thus the supervision can be always given to the contents of memory 4.
COPYRIGHT: (C)1980,JPO&Japio
JP11656978A 1978-09-25 1978-09-25 Microcomputer debug device Pending JPS5543660A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11656978A JPS5543660A (en) 1978-09-25 1978-09-25 Microcomputer debug device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11656978A JPS5543660A (en) 1978-09-25 1978-09-25 Microcomputer debug device

Publications (1)

Publication Number Publication Date
JPS5543660A true JPS5543660A (en) 1980-03-27

Family

ID=14690346

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11656978A Pending JPS5543660A (en) 1978-09-25 1978-09-25 Microcomputer debug device

Country Status (1)

Country Link
JP (1) JPS5543660A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4687231A (en) * 1984-12-20 1987-08-18 George Hartmann Gmbh & Co. Kg Identification card readable by a magnetic system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4687231A (en) * 1984-12-20 1987-08-18 George Hartmann Gmbh & Co. Kg Identification card readable by a magnetic system

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