JPS5538664A - Nonvolatile memory circuit - Google Patents

Nonvolatile memory circuit

Info

Publication number
JPS5538664A
JPS5538664A JP11117078A JP11117078A JPS5538664A JP S5538664 A JPS5538664 A JP S5538664A JP 11117078 A JP11117078 A JP 11117078A JP 11117078 A JP11117078 A JP 11117078A JP S5538664 A JPS5538664 A JP S5538664A
Authority
JP
Japan
Prior art keywords
transistor
write
read
nonvolatile memory
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11117078A
Other languages
Japanese (ja)
Other versions
JPS6223396B2 (en
Inventor
Minoru Hamada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP11117078A priority Critical patent/JPS5538664A/en
Publication of JPS5538664A publication Critical patent/JPS5538664A/en
Publication of JPS6223396B2 publication Critical patent/JPS6223396B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C14/00—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down

Landscapes

  • Read Only Memory (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)

Abstract

PURPOSE:To make it possible to write and read information at a high speed without limiting the number of rewriting operation by making nonvolatile the operation results of the dynamic memory of a MIS semiconductor nonvolatile memory transistor. CONSTITUTION:Binary information according to the ON-OFF operation of transistor Q2 corresponding to the charge in the floating capacity of control gate 17 of MIS transistor Q2 is read out through transistor Q3 to turn OFF transistor Q1 connected to gate 17. As a result, the write or refreshing operation of transistor Q2 is performed and transistor Q2 operates as a dynamic memory at a high speed. On the other hand, when transistor Q3 is turned ON by applying read digit line 12 with a voltage pulse of more than its critical voltage, gate 17 is charged; when the memory contents is ''1'', the threshold voltage of transistor Q2 never changes because a write voltage applied to drain 18 through transistor Q3 is high, and when ''0'', it does not change neither. As a result, information is stored in transistor Q2 even at power-OFF time and transistor Q2 operates as a nonvolatile memory, so that high-speed write and read operations can be performed without limiting the number of write operation.
JP11117078A 1978-09-08 1978-09-08 Nonvolatile memory circuit Granted JPS5538664A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11117078A JPS5538664A (en) 1978-09-08 1978-09-08 Nonvolatile memory circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11117078A JPS5538664A (en) 1978-09-08 1978-09-08 Nonvolatile memory circuit

Publications (2)

Publication Number Publication Date
JPS5538664A true JPS5538664A (en) 1980-03-18
JPS6223396B2 JPS6223396B2 (en) 1987-05-22

Family

ID=14554246

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11117078A Granted JPS5538664A (en) 1978-09-08 1978-09-08 Nonvolatile memory circuit

Country Status (1)

Country Link
JP (1) JPS5538664A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4495693A (en) * 1980-06-17 1985-01-29 Tokyo Shibaura Denki Kabushiki Kaisha Method of integrating MOS devices of double and single gate structure
JPS62266793A (en) * 1986-05-13 1987-11-19 Mitsubishi Electric Corp Nonvolatile semiconductor storage device
JPH03134894A (en) * 1989-10-19 1991-06-07 Sharp Corp Semiconductor memory device
WO1995019625A1 (en) * 1994-01-18 1995-07-20 Tadashi Shibata Semiconductor device
WO2011140044A2 (en) * 2010-05-06 2011-11-10 Micron Technology, Inc. Techniques for refreshing a semiconductor memory device
US9812179B2 (en) 2009-11-24 2017-11-07 Ovonyx Memory Technology, Llc Techniques for reducing disturbance in a semiconductor memory device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5152248A (en) * 1974-09-03 1976-05-08 Siemens Ag

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5152248A (en) * 1974-09-03 1976-05-08 Siemens Ag

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4495693A (en) * 1980-06-17 1985-01-29 Tokyo Shibaura Denki Kabushiki Kaisha Method of integrating MOS devices of double and single gate structure
JPS62266793A (en) * 1986-05-13 1987-11-19 Mitsubishi Electric Corp Nonvolatile semiconductor storage device
JPH0568799B2 (en) * 1986-05-13 1993-09-29 Mitsubishi Electric Corp
JPH03134894A (en) * 1989-10-19 1991-06-07 Sharp Corp Semiconductor memory device
WO1995019625A1 (en) * 1994-01-18 1995-07-20 Tadashi Shibata Semiconductor device
US9812179B2 (en) 2009-11-24 2017-11-07 Ovonyx Memory Technology, Llc Techniques for reducing disturbance in a semiconductor memory device
WO2011140044A2 (en) * 2010-05-06 2011-11-10 Micron Technology, Inc. Techniques for refreshing a semiconductor memory device
WO2011140044A3 (en) * 2010-05-06 2012-02-09 Micron Technology, Inc. Techniques for refreshing a semiconductor memory device
CN102884582A (en) * 2010-05-06 2013-01-16 美光科技公司 Techniques for refreshing a semiconductor memory device

Also Published As

Publication number Publication date
JPS6223396B2 (en) 1987-05-22

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