JPS5523674A - Correction circuit for intermediate frequency - Google Patents

Abstract

PURPOSE:To give the automatic tuning fine adjustment function by providing the detector detecting the shift of intermediate frequency, counter and prescaler with the radio receiver in PLL synthesizer system. CONSTITUTION:When the resonant frequency of the intermediate frequency stage IF is shifted, the detector 24 detects it via LPF 18 to output S3 or S4 depending on the shift of + or - to the center frequency. In this case, the mute signal S1 is outputted from the controller 21, and the output from the pulse generation circuit 27 is inputted to the clock terminal Cp of the counter 23 via the gates 25 and 26. The counter 23 makes up or down count to change the preset value and outputs it to the prescaler PS 12A. The PLL synthesizer S 20 counts down the input pulse, outputs the signal S2 every time when the frequency dividing value preset reaches 0, by taking it as the load signal of PS 12A. PS 12A is normally M notation counter, but it is tentatively X notation counter when the signal S2 is inputted, and it is repeated. Thus, the frequency dividing ratio of PLLS 20 can automatically be adjusted finely.