JPS55162141A - Multichannel memory system recorder - Google Patents

Multichannel memory system recorder

Info

Publication number
JPS55162141A
JPS55162141A JP7048979A JP7048979A JPS55162141A JP S55162141 A JPS55162141 A JP S55162141A JP 7048979 A JP7048979 A JP 7048979A JP 7048979 A JP7048979 A JP 7048979A JP S55162141 A JPS55162141 A JP S55162141A
Authority
JP
Japan
Prior art keywords
data
occurrence
signal
abnormality
input signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7048979A
Other languages
Japanese (ja)
Inventor
Shotaro Shindo
Hisao Nakane
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yokogawa Electric Corp
Original Assignee
Yokogawa Hokushin Electric Corp
Yokogawa Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yokogawa Hokushin Electric Corp, Yokogawa Electric Works Ltd filed Critical Yokogawa Hokushin Electric Corp
Priority to JP7048979A priority Critical patent/JPS55162141A/en
Publication of JPS55162141A publication Critical patent/JPS55162141A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To produce and record input signals before and after the occurrence of abnormality by updating and recording in a memory area a multichannel analog signal after converting it into a digital signal and then by stopping memory operation after storing data on a fixed number of a frequency when the abnormality occurs.
CONSTITUTION: A multichannel analog input signal is digitized by AD converting method 1 in a sufficient sampling period and the data are sequentially stored in the assigned area of RAM of data processor 2. On the basis of a command from commanding method 3, the data stored in circuit 2 are input to recording method 4 from the oldest data of a random channel in sequence. When the input signal becomes abnormal exceeding a set level, circuit 2 generates a trigger signal and, after data on the fixed number of times from abnormality occurrence are updated and recorded, stops a data memory unit. Under the set command of method 3, the data are sent out to method 4 in the storage order and input signal waveforms before and after the abnormality occurrence and the time of the abnormality occurrence are reproduced. Therefore, the method effective for a check on a signal in abnormarity occurrence can be obtained.
COPYRIGHT: (C)1980,JPO&Japio
JP7048979A 1979-06-04 1979-06-04 Multichannel memory system recorder Pending JPS55162141A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7048979A JPS55162141A (en) 1979-06-04 1979-06-04 Multichannel memory system recorder

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7048979A JPS55162141A (en) 1979-06-04 1979-06-04 Multichannel memory system recorder

Publications (1)

Publication Number Publication Date
JPS55162141A true JPS55162141A (en) 1980-12-17

Family

ID=13432974

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7048979A Pending JPS55162141A (en) 1979-06-04 1979-06-04 Multichannel memory system recorder

Country Status (1)

Country Link
JP (1) JPS55162141A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100484132B1 (en) * 2002-01-29 2005-04-18 삼성전자주식회사 Multi-channel A/D converter and system therewith

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100484132B1 (en) * 2002-01-29 2005-04-18 삼성전자주식회사 Multi-channel A/D converter and system therewith

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