JPS55153116A - Gain control system - Google Patents
Gain control systemInfo
- Publication number
- JPS55153116A JPS55153116A JP4398479A JP4398479A JPS55153116A JP S55153116 A JPS55153116 A JP S55153116A JP 4398479 A JP4398479 A JP 4398479A JP 4398479 A JP4398479 A JP 4398479A JP S55153116 A JPS55153116 A JP S55153116A
- Authority
- JP
- Japan
- Prior art keywords
- gain
- circuit
- comparator
- gain adjustment
- clock
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B5/00—Recording by magnetisation or demagnetisation of a record carrier; Reproducing by magnetic means; Record carriers therefor
- G11B5/02—Recording, reproducing, or erasing methods; Read, write or erase circuits therefor
Landscapes
- Digital Magnetic Recording (AREA)
- Signal Processing For Digital Recording And Reproducing (AREA)
- Control Of Amplification And Gain Control (AREA)
Abstract
PURPOSE:To make the best gain adjustment possible by a gain control system for a magnetic tape, by making fixed gain adjustment in amplitude reference area (ARA) and a data area. CONSTITUTION:Signals from magnetic head 1 are sent to differential amplifier 4 by way of amplifier 2 and gain change-over circuit 3. Its output is supplied to comparator 7 and demodulating circuit 5. Here, the signal amplitude of input line l of circuit 5 is held constant. In addition, down-counter 6 is set to a maximum count. Amplitude reference area ARA is read and read data are compared by comparator 7 to RRef to decrease the count of counter 6 gradually by making use of clock CL1, thereby adjusting the gain to a fixed reference level. At a slight interval from the point in time when a data block ends, clock CL2 is generated and on arrival of an output exceeding VRef of comparator 7, the steps of gain circuit 3 are changed. Therefore, the best gain adjustment can be made.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4398479A JPS55153116A (en) | 1979-04-11 | 1979-04-11 | Gain control system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4398479A JPS55153116A (en) | 1979-04-11 | 1979-04-11 | Gain control system |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS55153116A true JPS55153116A (en) | 1980-11-28 |
JPS6115508B2 JPS6115508B2 (en) | 1986-04-24 |
Family
ID=12678976
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4398479A Granted JPS55153116A (en) | 1979-04-11 | 1979-04-11 | Gain control system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS55153116A (en) |
-
1979
- 1979-04-11 JP JP4398479A patent/JPS55153116A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS6115508B2 (en) | 1986-04-24 |
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