JPS55140948A - Arithmetic unit - Google Patents

Abstract

PURPOSE: To realize reduction of the arithmetic steps and ensure the accurate arithmetic processing, by providing two units of reading addresses and a writing address each and independently to the memory device, thus realizing the high-speed processing.

CONSTITUTION: The 1st and 2nd memory devices 31 and 32 are provided to the memory element addressed to memory device 30, and the outputs of devices 31 and 32 are held at holding registers 51 and 52 for the section of one order word. The outputs of registers 51 and 52 are applied to the input of operator 40 to carry out the operation for the supplied data. At the same time, address selectors 61 and 62 are connected to devices 31 and 32, and the order words of order word generator 10 are given to selectors 61 and 62 plus operator 40. Then the clocks of clock generator 20, which gives a clock signal for one order word section to secure the address switching, the data writing and generation of the order word each, are applied to generator 10, selectors 61 and 62, device 30 plus operator 40 each. And the reading address of the input data is applied to operator 40 in the first half of the order word section; and the address where the output data of operator 40 is written into devices 31 and 32 is applied in the latter half of the order word section respectively.

COPYRIGHT: (C)1980,JPO&Japio