JPS55118153A - Operation processor - Google Patents
Operation processorInfo
- Publication number
- JPS55118153A JPS55118153A JP2528979A JP2528979A JPS55118153A JP S55118153 A JPS55118153 A JP S55118153A JP 2528979 A JP2528979 A JP 2528979A JP 2528979 A JP2528979 A JP 2528979A JP S55118153 A JPS55118153 A JP S55118153A
- Authority
- JP
- Japan
- Prior art keywords
- field
- register
- coincidence
- circuit
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
PURPOSE: To increase the processing speed by giving the NOP (operation) action when the coincidence of the contents is obtained between the signal source field and the result storage destination field and at the same time transmitting the data possessed by the register to other process control part as well.
CONSTITUTION: The unit which executes register transfer orders MOVRi and Rk possesses comparator circuit 7 which gives the comparison to the contents between the signal source field and the result storage destination field. For circuit 7, bit signals SC1WSCn forming the signal field plus bit signals DS1WDSn forming the result storage destination field are connected to the input ends of n units of exclusive NOR gate 10. And the output is supplied to AND gate 11 to deliver coincidence signal 12. When the coincidence of the contents is obtained between the both field, i.e., Ri=Rk is obtained, the coincidence signal is sent to gate circuit 8. Circuit 8 sends the data from register Ri to register Rk and also transfers to other process mechanism.
COPYRIGHT: (C)1980,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2528979A JPS55118153A (en) | 1979-03-05 | 1979-03-05 | Operation processor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2528979A JPS55118153A (en) | 1979-03-05 | 1979-03-05 | Operation processor |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS55118153A true JPS55118153A (en) | 1980-09-10 |
JPS6136256B2 JPS6136256B2 (en) | 1986-08-18 |
Family
ID=12161850
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2528979A Granted JPS55118153A (en) | 1979-03-05 | 1979-03-05 | Operation processor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS55118153A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0298733A (en) * | 1988-10-06 | 1990-04-11 | Nec Corp | Information processor |
USRE40498E1 (en) | 1993-05-27 | 2008-09-09 | Matsushita Electric Industrial Co., Ltd. | Variable address length compiler and processor improved in address management |
-
1979
- 1979-03-05 JP JP2528979A patent/JPS55118153A/en active Granted
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0298733A (en) * | 1988-10-06 | 1990-04-11 | Nec Corp | Information processor |
USRE40498E1 (en) | 1993-05-27 | 2008-09-09 | Matsushita Electric Industrial Co., Ltd. | Variable address length compiler and processor improved in address management |
USRE41959E1 (en) | 1993-05-27 | 2010-11-23 | Panasonic Corporation | Variable address length compiler and processor improved in address management |
Also Published As
Publication number | Publication date |
---|---|
JPS6136256B2 (en) | 1986-08-18 |
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