JPS55116141A - Logical operation controller - Google Patents
Logical operation controllerInfo
- Publication number
- JPS55116141A JPS55116141A JP2320279A JP2320279A JPS55116141A JP S55116141 A JPS55116141 A JP S55116141A JP 2320279 A JP2320279 A JP 2320279A JP 2320279 A JP2320279 A JP 2320279A JP S55116141 A JPS55116141 A JP S55116141A
- Authority
- JP
- Japan
- Prior art keywords
- logical operation
- instruction
- memory
- icus
- operations
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Executing Machine-Instructions (AREA)
- Programmable Controllers (AREA)
Abstract
PURPOSE: To realize a miniature, low-priced and efficient logical operation controller with memory capacity reduced by operating one-bit logical operation units in parallel and then by controlling the clock signal of each logical operation unit.
CONSTITUTION: Program counter PC sends an address signal for an instruction to be executed to program memory PM stored with executive instructions to read the instruction, which is supplied to one-bit logical operation units ICU1WICU3. Then, ICU1WICU3 put arithmetic into effect and write or read the results into or from data memory DM at an address position indicated by PM by way of buffer BUF. When one of ICUs sends a jump instruction, clock signals of two other ICUs are cut off and their following operations are inhibited. Once a return instruction is sent out, the transmission of the clock signals are restarted and the interrupted operations of ICUs are also restarted. As a result, the need for a memory for no- operation instructions is eliminated and the memory capacity can be reduced, so that the operations can be made efficient.
COPYRIGHT: (C)1980,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2320279A JPS55116141A (en) | 1979-02-28 | 1979-02-28 | Logical operation controller |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2320279A JPS55116141A (en) | 1979-02-28 | 1979-02-28 | Logical operation controller |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS55116141A true JPS55116141A (en) | 1980-09-06 |
Family
ID=12104075
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2320279A Pending JPS55116141A (en) | 1979-02-28 | 1979-02-28 | Logical operation controller |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS55116141A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7774581B2 (en) | 2007-03-23 | 2010-08-10 | Samsung Electronics Co., Ltd. | Apparatus for compressing instruction word for parallel processing VLIW computer and method for the same |
-
1979
- 1979-02-28 JP JP2320279A patent/JPS55116141A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7774581B2 (en) | 2007-03-23 | 2010-08-10 | Samsung Electronics Co., Ltd. | Apparatus for compressing instruction word for parallel processing VLIW computer and method for the same |
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