JPS55113200A - Checking method for ic memory - Google Patents
Checking method for ic memoryInfo
- Publication number
- JPS55113200A JPS55113200A JP2041879A JP2041879A JPS55113200A JP S55113200 A JPS55113200 A JP S55113200A JP 2041879 A JP2041879 A JP 2041879A JP 2041879 A JP2041879 A JP 2041879A JP S55113200 A JPS55113200 A JP S55113200A
- Authority
- JP
- Japan
- Prior art keywords
- defective
- information
- memory
- test pattern
- analysis
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
- Tests Of Electronic Circuits (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
PURPOSE: To improve the efficiency of defective analysis by storing position information about a defective memory cell together with a decision result using a test pattern.
CONSTITUTION: Address information from test pattern generator 1 is supplied to MUT10 and fail memory 11 in parallel and test pattern information is compared with the output of MUT10 to make decision 13. On the other hand, before a test pattern run, information in program counter 3 is compared 14 with the content of register 5 where the count position of counter 3 can be preset and when the both agree with each other, a synchronizing signal is generated. Only when a defective signal of decision circuit 13 and the synchronizing signal are generated at the same time, defective information is written in memory 11. The address of a defective cell can therefore be found by reading memory information in memory 11 during analysis. Thus, the efficiency of defective analysis can be improved.
COPYRIGHT: (C)1980,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2041879A JPS55113200A (en) | 1979-02-22 | 1979-02-22 | Checking method for ic memory |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2041879A JPS55113200A (en) | 1979-02-22 | 1979-02-22 | Checking method for ic memory |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS55113200A true JPS55113200A (en) | 1980-09-01 |
JPS6141080B2 JPS6141080B2 (en) | 1986-09-12 |
Family
ID=12026478
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2041879A Granted JPS55113200A (en) | 1979-02-22 | 1979-02-22 | Checking method for ic memory |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS55113200A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57164497A (en) * | 1981-03-31 | 1982-10-09 | Toshiba Corp | Controlling device of address fail memory |
JPS6050698A (en) * | 1983-08-26 | 1985-03-20 | Mitsubishi Electric Corp | Semiconductor testing device |
JPS60106100A (en) * | 1983-11-15 | 1985-06-11 | Fujitsu Ltd | Testing system of semiconductor memory |
US5317573A (en) * | 1989-08-30 | 1994-05-31 | International Business Machines Corporation | Apparatus and method for real time data error capture and compression redundancy analysis |
JP2007172778A (en) * | 2005-12-26 | 2007-07-05 | Nec Electronics Corp | Memory test circuit and memory test method |
-
1979
- 1979-02-22 JP JP2041879A patent/JPS55113200A/en active Granted
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57164497A (en) * | 1981-03-31 | 1982-10-09 | Toshiba Corp | Controlling device of address fail memory |
JPS6232559B2 (en) * | 1981-03-31 | 1987-07-15 | Tokyo Shibaura Electric Co | |
JPS6050698A (en) * | 1983-08-26 | 1985-03-20 | Mitsubishi Electric Corp | Semiconductor testing device |
JPS60106100A (en) * | 1983-11-15 | 1985-06-11 | Fujitsu Ltd | Testing system of semiconductor memory |
US5317573A (en) * | 1989-08-30 | 1994-05-31 | International Business Machines Corporation | Apparatus and method for real time data error capture and compression redundancy analysis |
JP2007172778A (en) * | 2005-12-26 | 2007-07-05 | Nec Electronics Corp | Memory test circuit and memory test method |
Also Published As
Publication number | Publication date |
---|---|
JPS6141080B2 (en) | 1986-09-12 |
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