JPS55112658A - Detection circuit of continuous code - Google Patents

Detection circuit of continuous code

Info

Publication number
JPS55112658A
JPS55112658A JP2044779A JP2044779A JPS55112658A JP S55112658 A JPS55112658 A JP S55112658A JP 2044779 A JP2044779 A JP 2044779A JP 2044779 A JP2044779 A JP 2044779A JP S55112658 A JPS55112658 A JP S55112658A
Authority
JP
Japan
Prior art keywords
signal
clock
continuity
output
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2044779A
Other languages
Japanese (ja)
Inventor
Tatsuo Umetsu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP2044779A priority Critical patent/JPS55112658A/en
Publication of JPS55112658A publication Critical patent/JPS55112658A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To enable to detect the continuity of "0" for a given period of input signal with a simple constitution, by reading out the "0" level of input signal with the first FF and reading out the output with the second FF in the advanced clock.
CONSTITUTION: In the unit handling digital signal, when the continuity of zero code is, for example, detected, FF1 is reset when the signal input is "1" and the output terminal Q is "0" level. Further, when the clock b having lower frequency than the fundametnal repetitive period of the signal a is fed to the terminal T of FF1, FF1 delivers "1" to the output terminal Q every leading time of the clock b. In this case, "1" is caused when the input signal a is "0" to the reset terminal, and it continues unit "1" is incoming to the signal a. The Q output is read out with FF2 by the clock d advanced with the rate of the delay circuit 3 of FF1. Thus, the continuity of "0" for a given period of the signal a can be detected with a simple constitution.
COPYRIGHT: (C)1980,JPO&Japio
JP2044779A 1979-02-22 1979-02-22 Detection circuit of continuous code Pending JPS55112658A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2044779A JPS55112658A (en) 1979-02-22 1979-02-22 Detection circuit of continuous code

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2044779A JPS55112658A (en) 1979-02-22 1979-02-22 Detection circuit of continuous code

Publications (1)

Publication Number Publication Date
JPS55112658A true JPS55112658A (en) 1980-08-30

Family

ID=12027303

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2044779A Pending JPS55112658A (en) 1979-02-22 1979-02-22 Detection circuit of continuous code

Country Status (1)

Country Link
JP (1) JPS55112658A (en)

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