JPS55112621A - Clock unit for information processing system - Google Patents

Clock unit for information processing system

Info

Publication number
JPS55112621A
JPS55112621A JP1834179A JP1834179A JPS55112621A JP S55112621 A JPS55112621 A JP S55112621A JP 1834179 A JP1834179 A JP 1834179A JP 1834179 A JP1834179 A JP 1834179A JP S55112621 A JPS55112621 A JP S55112621A
Authority
JP
Japan
Prior art keywords
clock
timer
unit
circuit
csc3
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1834179A
Other languages
Japanese (ja)
Inventor
Hidekazu Minami
Masanori Hirano
Naoaki Yasumi
Yuichi Narita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Hitachi Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Original Assignee
Fujitsu Ltd
Hitachi Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Hitachi Ltd, NEC Corp, Nippon Telegraph and Telephone Corp, Nippon Electric Co Ltd filed Critical Fujitsu Ltd
Priority to JP1834179A priority Critical patent/JPS55112621A/en
Publication of JPS55112621A publication Critical patent/JPS55112621A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To enable the clock operation by the second unit even if the first unit is in failure, by incorporating the real time timer to each unit, in the information processing system consisting of the first unit and a plurality of the second units.
CONSTITUTION: In the system consisting of the centralized monitor unit CSC3 and a plurality of CPU4, each unit incorporates the real timers 2, 1 respectively. The timer 2 counts the real time standard value of the timer 1 via the clock set instruction line 18 and the timer value supply line 15. If the CSC3 is normal, the signal of the clock effective display line 17 is 1, the selection circuit 11 selects the clock of the clock generation circuit 5, and if the CSC3 is in failure, the signal on the line 17 is 0 with the failure detection circuit 6, and the circuit 11 selects the clock of the clock generating circuit 12. The clock count clock from the circuit 11 is fed to the timer 1 via the timer control circuit 10.
COPYRIGHT: (C)1980,JPO&Japio
JP1834179A 1979-02-21 1979-02-21 Clock unit for information processing system Pending JPS55112621A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1834179A JPS55112621A (en) 1979-02-21 1979-02-21 Clock unit for information processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1834179A JPS55112621A (en) 1979-02-21 1979-02-21 Clock unit for information processing system

Publications (1)

Publication Number Publication Date
JPS55112621A true JPS55112621A (en) 1980-08-30

Family

ID=11968945

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1834179A Pending JPS55112621A (en) 1979-02-21 1979-02-21 Clock unit for information processing system

Country Status (1)

Country Link
JP (1) JPS55112621A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1991016671A1 (en) * 1990-04-13 1991-10-31 Kabushiki Kaisha Toshiba Clock device
JPH0826366A (en) * 1994-07-18 1996-01-30 Toshiba Emi Ltd Disk housing case

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1991016671A1 (en) * 1990-04-13 1991-10-31 Kabushiki Kaisha Toshiba Clock device
JPH0826366A (en) * 1994-07-18 1996-01-30 Toshiba Emi Ltd Disk housing case

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