JPS55110427A - Clamp circuit - Google Patents

Clamp circuit

Info

Publication number
JPS55110427A
JPS55110427A JP1813079A JP1813079A JPS55110427A JP S55110427 A JPS55110427 A JP S55110427A JP 1813079 A JP1813079 A JP 1813079A JP 1813079 A JP1813079 A JP 1813079A JP S55110427 A JPS55110427 A JP S55110427A
Authority
JP
Japan
Prior art keywords
signal
amplifier
regeneration
noise
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1813079A
Other languages
Japanese (ja)
Inventor
Shinichi Kitamura
Takashi Tsuda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP1813079A priority Critical patent/JPS55110427A/en
Publication of JPS55110427A publication Critical patent/JPS55110427A/en
Pending legal-status Critical Current

Links

Landscapes

  • Manipulation Of Pulses (AREA)
  • Dc Digital Transmission (AREA)

Abstract

PURPOSE: To enable DC regeneration without being subject to the effect of noise, by low pass filtering which rejects noise in the signal for a given clamp region only.
CONSTITUTION: In the clamp circuit used for DC regeneration of signal in AC transmission, the buffer amplifiers A1, A2 and A3 have higher input impedance, the output impedance is lower, and especially the amplifier A3 can make DC transmission. Further, the signal A is inputted to the amplifier A1 and LPF consisting of the resistor R1 and capacitor C1, the switch S1 is closed with the control signal B for a given period T1 to output the signal C. This signal C enters the amplifier A2 and is clamped D for a given period T2 with the switch S2 at the clamp section CLP. Further, the output signal E obtained from the amplifier A3 allows to reject the effect of noise for DC regeneration.
COPYRIGHT: (C)1980,JPO&Japio
JP1813079A 1979-02-19 1979-02-19 Clamp circuit Pending JPS55110427A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1813079A JPS55110427A (en) 1979-02-19 1979-02-19 Clamp circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1813079A JPS55110427A (en) 1979-02-19 1979-02-19 Clamp circuit

Publications (1)

Publication Number Publication Date
JPS55110427A true JPS55110427A (en) 1980-08-25

Family

ID=11963018

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1813079A Pending JPS55110427A (en) 1979-02-19 1979-02-19 Clamp circuit

Country Status (1)

Country Link
JP (1) JPS55110427A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5615160U (en) * 1979-07-16 1981-02-09
JPS6080348A (en) * 1983-10-07 1985-05-08 Nec Corp Offset compensating circuit

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5615160U (en) * 1979-07-16 1981-02-09
JPS6128442Y2 (en) * 1979-07-16 1986-08-23
JPS6080348A (en) * 1983-10-07 1985-05-08 Nec Corp Offset compensating circuit
JPH0320097B2 (en) * 1983-10-07 1991-03-18 Nippon Denki Kk

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