JPS55107246A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS55107246A
JPS55107246A JP1374379A JP1374379A JPS55107246A JP S55107246 A JPS55107246 A JP S55107246A JP 1374379 A JP1374379 A JP 1374379A JP 1374379 A JP1374379 A JP 1374379A JP S55107246 A JPS55107246 A JP S55107246A
Authority
JP
Japan
Prior art keywords
layer
substrate
wiring
gas
hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1374379A
Other languages
Japanese (ja)
Inventor
Shohei Shima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CHIYOU LSI GIJUTSU KENKYU KUMIAI
CHO LSI GIJUTSU KENKYU KUMIAI
Original Assignee
CHIYOU LSI GIJUTSU KENKYU KUMIAI
CHO LSI GIJUTSU KENKYU KUMIAI
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CHIYOU LSI GIJUTSU KENKYU KUMIAI, CHO LSI GIJUTSU KENKYU KUMIAI filed Critical CHIYOU LSI GIJUTSU KENKYU KUMIAI
Priority to JP1374379A priority Critical patent/JPS55107246A/en
Publication of JPS55107246A publication Critical patent/JPS55107246A/en
Pending legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: To provide an opening in a taper shape on a region including an Al wiring layer by a method wherein a SiN layer is formed by gradually reducing plasma power.
CONSTITUTION: An Al layer is provided on a Si substrate 11 wherein an element has been formed, and a flat Al wiring layer 13 whose periphery is filled with a porous alumina layer 12 through selective anodic oxidation. Next the substrate 11 is placed in the apparatus, while supplying it with, for instance, 75cc/min of a SiH4 gas, 300cc/min of NH3 and 0.6l/min of an Ar gas, and letting the substrate react in the plasma, so that the plasma power is successively reduced for the formation of a SiN film 14. The film formed by this method shows faster etching speed in a portion nearer to the surface. Followed by this process, if the SiN film 14 is provided with a resist mask, before being etched by a liquid of fluoric acid series, a through hole 15 with a cone-shaped taper is formed. Then if the Al wiring 16 is formed in the hole, disconnection of wire can be avoided.
COPYRIGHT: (C)1980,JPO&Japio
JP1374379A 1979-02-08 1979-02-08 Manufacture of semiconductor device Pending JPS55107246A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1374379A JPS55107246A (en) 1979-02-08 1979-02-08 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1374379A JPS55107246A (en) 1979-02-08 1979-02-08 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS55107246A true JPS55107246A (en) 1980-08-16

Family

ID=11841734

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1374379A Pending JPS55107246A (en) 1979-02-08 1979-02-08 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS55107246A (en)

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