JPS5484947A - Data line changeover system - Google Patents

Data line changeover system

Info

Publication number
JPS5484947A
JPS5484947A JP15308377A JP15308377A JPS5484947A JP S5484947 A JPS5484947 A JP S5484947A JP 15308377 A JP15308377 A JP 15308377A JP 15308377 A JP15308377 A JP 15308377A JP S5484947 A JPS5484947 A JP S5484947A
Authority
JP
Japan
Prior art keywords
unit
data line
cpu
line
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15308377A
Other languages
Japanese (ja)
Inventor
Akitoshi Hara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP15308377A priority Critical patent/JPS5484947A/en
Publication of JPS5484947A publication Critical patent/JPS5484947A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To increases the reliability of selection system, by surely blocking the reception of error data at the data line selection, through the addition of a simple hardware set without giving any burden to the software.
CONSTITUTION: In the information processing system commonly using the peripheral unit for a plurality of processors, the data line selector 104 is placed between the data lines L1 and L2 of a plurality of CPU's 101 and 102 and the data line L3 of the peripheral unit 103. The isolation circuits RD1 and RD2 receiving the usage request signals RO1 and RO2 of the unit unit 103 from CPU's 101 and 102 and relays K1 to K3 operated with the output of the circuits RD1 and RD2 are provided. The operation of the relays K1 to K3 is selected with the request signals RQ1 and RQ2, forming the circuit of control signal line Lc, and the reception of the output of the line receiver RL of the unit 103 is inhibited with the gates G1 and G2. Further, the selection of the output of the line drivers DR1 and RD2 of CPU'S 101 and 102 simultaneously are made.
COPYRIGHT: (C)1979,JPO&Japio
JP15308377A 1977-12-20 1977-12-20 Data line changeover system Pending JPS5484947A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15308377A JPS5484947A (en) 1977-12-20 1977-12-20 Data line changeover system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15308377A JPS5484947A (en) 1977-12-20 1977-12-20 Data line changeover system

Publications (1)

Publication Number Publication Date
JPS5484947A true JPS5484947A (en) 1979-07-06

Family

ID=15554596

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15308377A Pending JPS5484947A (en) 1977-12-20 1977-12-20 Data line changeover system

Country Status (1)

Country Link
JP (1) JPS5484947A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63296534A (en) * 1987-05-28 1988-12-02 Nec Corp Directional path establishing system

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4874146A (en) * 1971-12-29 1973-10-05

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4874146A (en) * 1971-12-29 1973-10-05

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63296534A (en) * 1987-05-28 1988-12-02 Nec Corp Directional path establishing system

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