JPS5457918A - Memory access processing system - Google Patents

Memory access processing system

Info

Publication number
JPS5457918A
JPS5457918A JP12480377A JP12480377A JPS5457918A JP S5457918 A JPS5457918 A JP S5457918A JP 12480377 A JP12480377 A JP 12480377A JP 12480377 A JP12480377 A JP 12480377A JP S5457918 A JPS5457918 A JP S5457918A
Authority
JP
Japan
Prior art keywords
write
cpu1
time
register
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12480377A
Other languages
Japanese (ja)
Other versions
JPS5821737B2 (en
Inventor
Kunihiko Hakamazuka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP52124803A priority Critical patent/JPS5821737B2/en
Publication of JPS5457918A publication Critical patent/JPS5457918A/en
Publication of JPS5821737B2 publication Critical patent/JPS5821737B2/en
Expired legal-status Critical Current

Links

Abstract

PURPOSE: To improve the processing speed of the whole of the system by using a shortened one-CPU cycle at a write access time, by providing a write data register in a memory.
CONSTITUTION: Write data register 6 where write data transmitted from CPU1 is set, at least, until the end time of a one-CPU cycle period is provided in memory 3, and further, write instructing signal generation part 9 which generates a signal instructing the write of contents of register 6 at the initial time of the next one-CPU cycle is provided. CPU1 is operated by clocks corresponding to shortened one-CPU cycles at a write access time and sets write data to register 6 so that CPU1 may be disconnected from the write access operation to memory 3. As a result, the time which CPU1 requires for the write access processing is shortened, and the proces- sing speed of the whole of the system is enhanced
COPYRIGHT: (C)1979,JPO&Japio
JP52124803A 1977-10-18 1977-10-18 Memory access processing method Expired JPS5821737B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP52124803A JPS5821737B2 (en) 1977-10-18 1977-10-18 Memory access processing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP52124803A JPS5821737B2 (en) 1977-10-18 1977-10-18 Memory access processing method

Publications (2)

Publication Number Publication Date
JPS5457918A true JPS5457918A (en) 1979-05-10
JPS5821737B2 JPS5821737B2 (en) 1983-05-02

Family

ID=14894504

Family Applications (1)

Application Number Title Priority Date Filing Date
JP52124803A Expired JPS5821737B2 (en) 1977-10-18 1977-10-18 Memory access processing method

Country Status (1)

Country Link
JP (1) JPS5821737B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62168246A (en) * 1986-01-20 1987-07-24 Fujitsu Ltd Memory writing control system

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5034134A (en) * 1973-07-27 1975-04-02
JPS513138A (en) * 1974-06-25 1976-01-12 Nippon Electric Co Kiokusochino seigyojohohojihoshiki
JPS5222438A (en) * 1975-08-13 1977-02-19 Nec Corp Method of generating timing of memory

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5034134A (en) * 1973-07-27 1975-04-02
JPS513138A (en) * 1974-06-25 1976-01-12 Nippon Electric Co Kiokusochino seigyojohohojihoshiki
JPS5222438A (en) * 1975-08-13 1977-02-19 Nec Corp Method of generating timing of memory

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62168246A (en) * 1986-01-20 1987-07-24 Fujitsu Ltd Memory writing control system

Also Published As

Publication number Publication date
JPS5821737B2 (en) 1983-05-02

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