JPS5457918A - Memory access processing system - Google Patents
Memory access processing systemInfo
- Publication number
- JPS5457918A JPS5457918A JP12480377A JP12480377A JPS5457918A JP S5457918 A JPS5457918 A JP S5457918A JP 12480377 A JP12480377 A JP 12480377A JP 12480377 A JP12480377 A JP 12480377A JP S5457918 A JPS5457918 A JP S5457918A
- Authority
- JP
- Japan
- Prior art keywords
- write
- cpu1
- time
- register
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
PURPOSE: To improve the processing speed of the whole of the system by using a shortened one-CPU cycle at a write access time, by providing a write data register in a memory.
CONSTITUTION: Write data register 6 where write data transmitted from CPU1 is set, at least, until the end time of a one-CPU cycle period is provided in memory 3, and further, write instructing signal generation part 9 which generates a signal instructing the write of contents of register 6 at the initial time of the next one-CPU cycle is provided. CPU1 is operated by clocks corresponding to shortened one-CPU cycles at a write access time and sets write data to register 6 so that CPU1 may be disconnected from the write access operation to memory 3. As a result, the time which CPU1 requires for the write access processing is shortened, and the proces- sing speed of the whole of the system is enhanced
COPYRIGHT: (C)1979,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP52124803A JPS5821737B2 (en) | 1977-10-18 | 1977-10-18 | Memory access processing method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP52124803A JPS5821737B2 (en) | 1977-10-18 | 1977-10-18 | Memory access processing method |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5457918A true JPS5457918A (en) | 1979-05-10 |
JPS5821737B2 JPS5821737B2 (en) | 1983-05-02 |
Family
ID=14894504
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP52124803A Expired JPS5821737B2 (en) | 1977-10-18 | 1977-10-18 | Memory access processing method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5821737B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62168246A (en) * | 1986-01-20 | 1987-07-24 | Fujitsu Ltd | Memory writing control system |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5034134A (en) * | 1973-07-27 | 1975-04-02 | ||
JPS513138A (en) * | 1974-06-25 | 1976-01-12 | Nippon Electric Co | Kiokusochino seigyojohohojihoshiki |
JPS5222438A (en) * | 1975-08-13 | 1977-02-19 | Nec Corp | Method of generating timing of memory |
-
1977
- 1977-10-18 JP JP52124803A patent/JPS5821737B2/en not_active Expired
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5034134A (en) * | 1973-07-27 | 1975-04-02 | ||
JPS513138A (en) * | 1974-06-25 | 1976-01-12 | Nippon Electric Co | Kiokusochino seigyojohohojihoshiki |
JPS5222438A (en) * | 1975-08-13 | 1977-02-19 | Nec Corp | Method of generating timing of memory |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62168246A (en) * | 1986-01-20 | 1987-07-24 | Fujitsu Ltd | Memory writing control system |
Also Published As
Publication number | Publication date |
---|---|
JPS5821737B2 (en) | 1983-05-02 |
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