JPS5447561A - Analog/digital interface circuit - Google Patents

Analog/digital interface circuit

Info

Publication number
JPS5447561A
JPS5447561A JP11417277A JP11417277A JPS5447561A JP S5447561 A JPS5447561 A JP S5447561A JP 11417277 A JP11417277 A JP 11417277A JP 11417277 A JP11417277 A JP 11417277A JP S5447561 A JPS5447561 A JP S5447561A
Authority
JP
Japan
Prior art keywords
clock
analog
circuit
interface circuit
supplied
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11417277A
Other languages
Japanese (ja)
Inventor
Masao Yamazawa
Tetsuo Soejima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP11417277A priority Critical patent/JPS5447561A/en
Publication of JPS5447561A publication Critical patent/JPS5447561A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To obtain an economical interface circuit by supplying the clock obtained by dividing the multiplying clock to the analog part and supplying the clock which becomes toothless at the frame synchronous pulse position to the digital part respectively.
CONSTITUTION: The clock of frequency f2 to be supplied to multiplying part 14 is n-divided through frame synchronizing circuit 15, and the clock of f2/n frequency is applied to analog interface part 12a of interface circuit 12 as well as to inhibition gate 16. The inhibition signal of gate 16 uses signal (a) at the position of the frame synchronous pulse. Accordingly, clock f1 containing the fixed and toothless frame syncronous information is supplied to part 12b of circuit 12 as well as to digital circuit 13. While the clock freturing a fixed pulse duration at all times is supplied to part 12a. Thus, the steady analog signal process is carried out, obtaining a highly economical and practical interface circuit
COPYRIGHT: (C)1979,JPO&Japio
JP11417277A 1977-09-22 1977-09-22 Analog/digital interface circuit Pending JPS5447561A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11417277A JPS5447561A (en) 1977-09-22 1977-09-22 Analog/digital interface circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11417277A JPS5447561A (en) 1977-09-22 1977-09-22 Analog/digital interface circuit

Publications (1)

Publication Number Publication Date
JPS5447561A true JPS5447561A (en) 1979-04-14

Family

ID=14630969

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11417277A Pending JPS5447561A (en) 1977-09-22 1977-09-22 Analog/digital interface circuit

Country Status (1)

Country Link
JP (1) JPS5447561A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57129020A (en) * 1981-02-04 1982-08-10 Hitachi Ltd Signal processing circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57129020A (en) * 1981-02-04 1982-08-10 Hitachi Ltd Signal processing circuit
JPS6343929B2 (en) * 1981-02-04 1988-09-01 Hitachi Seisakusho Kk

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