JPS5443650A - Memory control method of electronic computer - Google Patents

Memory control method of electronic computer

Info

Publication number
JPS5443650A
JPS5443650A JP10983977A JP10983977A JPS5443650A JP S5443650 A JPS5443650 A JP S5443650A JP 10983977 A JP10983977 A JP 10983977A JP 10983977 A JP10983977 A JP 10983977A JP S5443650 A JPS5443650 A JP S5443650A
Authority
JP
Japan
Prior art keywords
data
numeric data
information
display
defective
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10983977A
Other languages
Japanese (ja)
Inventor
Mario Uesugi
Chuji Shibata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP10983977A priority Critical patent/JPS5443650A/en
Publication of JPS5443650A publication Critical patent/JPS5443650A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To improve response with shortening the display change time dependent upon defective information at a numeric data display time on CRT, by storing numeric data and the detective state of this data in a two-word continuous memory area in the power system controlling computer system.
CONSTITUTION: In the power system controlling computer system, numeric data memory table 1 and ddefective state memory table 2 are stored in two-word continuous numeric data defective state memory table 3 in the computer which is provided with input device 6 to input transmitted information, CPU4 and auxiliary memory 7 which store inputted information data, processed and calculated data and calculated data indicating whether these data are good or not, and color CRT8 to display stored data. Then, the change time at the time when numeric data displayed on CRT8 is subjected to display change dependently upon defective information is shortened.
COPYRIGHT: (C)1979,JPO&Japio
JP10983977A 1977-09-14 1977-09-14 Memory control method of electronic computer Pending JPS5443650A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10983977A JPS5443650A (en) 1977-09-14 1977-09-14 Memory control method of electronic computer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10983977A JPS5443650A (en) 1977-09-14 1977-09-14 Memory control method of electronic computer

Publications (1)

Publication Number Publication Date
JPS5443650A true JPS5443650A (en) 1979-04-06

Family

ID=14520501

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10983977A Pending JPS5443650A (en) 1977-09-14 1977-09-14 Memory control method of electronic computer

Country Status (1)

Country Link
JP (1) JPS5443650A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56132465A (en) * 1980-02-20 1981-10-16 Bosch Gmbh Robert Circuit device for igniting internal combustion engine
US4954685A (en) * 1987-07-31 1990-09-04 Tokyo Electron Limited Heating furnace for semiconductor wafers

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56132465A (en) * 1980-02-20 1981-10-16 Bosch Gmbh Robert Circuit device for igniting internal combustion engine
US4954685A (en) * 1987-07-31 1990-09-04 Tokyo Electron Limited Heating furnace for semiconductor wafers

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