JPS5434752A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5434752A
JPS5434752A JP10187777A JP10187777A JPS5434752A JP S5434752 A JPS5434752 A JP S5434752A JP 10187777 A JP10187777 A JP 10187777A JP 10187777 A JP10187777 A JP 10187777A JP S5434752 A JPS5434752 A JP S5434752A
Authority
JP
Japan
Prior art keywords
manufacture
semiconductor device
conductive film
flank
pellets
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10187777A
Other languages
Japanese (ja)
Inventor
Yasuo Higami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Home Electronics Ltd
NEC Corp
Original Assignee
NEC Home Electronics Ltd
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Home Electronics Ltd, Nippon Electric Co Ltd filed Critical NEC Home Electronics Ltd
Priority to JP10187777A priority Critical patent/JPS5434752A/en
Publication of JPS5434752A publication Critical patent/JPS5434752A/en
Pending legal-status Critical Current

Links

Landscapes

  • Dicing (AREA)

Abstract

PURPOSE: To make a semiconductor substrate into pellets while making it possible to disconnect a conductive film completely and also preventing the conductive film from sticking to the flank.
COPYRIGHT: (C)1979,JPO&Japio
JP10187777A 1977-08-24 1977-08-24 Manufacture of semiconductor device Pending JPS5434752A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10187777A JPS5434752A (en) 1977-08-24 1977-08-24 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10187777A JPS5434752A (en) 1977-08-24 1977-08-24 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5434752A true JPS5434752A (en) 1979-03-14

Family

ID=14312182

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10187777A Pending JPS5434752A (en) 1977-08-24 1977-08-24 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5434752A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5835982A (en) * 1981-08-28 1983-03-02 Hitachi Ltd Manufacture of semiconductor pressure sensor
WO1992009098A2 (en) * 1990-11-05 1992-05-29 Harris Corporation Process for forming extremely thin integrated circuit dice
CN112970106A (en) * 2018-11-12 2021-06-15 Hrl实验室有限责任公司 Method for designing and uniformly co-fabricating small vias and large cavities through a substrate

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5133985A (en) * 1974-09-17 1976-03-23 Mitsubishi Electric Corp Handotaisochi no seizohoho

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5133985A (en) * 1974-09-17 1976-03-23 Mitsubishi Electric Corp Handotaisochi no seizohoho

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5835982A (en) * 1981-08-28 1983-03-02 Hitachi Ltd Manufacture of semiconductor pressure sensor
JPH0419712B2 (en) * 1981-08-28 1992-03-31 Hitachi Ltd
WO1992009098A2 (en) * 1990-11-05 1992-05-29 Harris Corporation Process for forming extremely thin integrated circuit dice
WO1992009098A3 (en) * 1990-11-05 1992-07-09 Harris Corp Process for forming extremely thin integrated circuit dice
CN112970106A (en) * 2018-11-12 2021-06-15 Hrl实验室有限责任公司 Method for designing and uniformly co-fabricating small vias and large cavities through a substrate

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