JPS54155770A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS54155770A JPS54155770A JP6467678A JP6467678A JPS54155770A JP S54155770 A JPS54155770 A JP S54155770A JP 6467678 A JP6467678 A JP 6467678A JP 6467678 A JP6467678 A JP 6467678A JP S54155770 A JPS54155770 A JP S54155770A
- Authority
- JP
- Japan
- Prior art keywords
- strain
- substrate
- layer
- epitaxial layer
- polished
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
PURPOSE: To improve electric characteristics with strain in an element region eliminated, by heat-treating the reverse surface of a semiconductor substrate, with a semiconductor element on its top surface, at a temperature of more than 200°C after mechanically polishing the reverse surface to a fixed thickness.
CONSTITUTION: On semiconductor substrate 1, epitaxial layer is grown, the surface is covered with oxidized film 3, and after base region 4 and emitter region 5 are both provided, metal electrode 6 is fitted. The reverse surface of substrate 1 of the semiconductor device formed in this way is mechanically polished to a thickness suitable for pelletizing, thereby generating strain between substrate 1 and epitaxial layer 2. In other words, plastic strain layer 11 close to polished surface 7, plastic- elastic strain layer 12 from its top closely to the surface of substrate 1, and elastic strain layer 13 from its top to the surface of epitaxial layer 2 are formed respectively. Next, a heat treatment of 400W500°C is done in N2 gas for sixty minutes to remove strain completely except elastic strain layer 12 near polished surface 7. Consequently, the manufacture yield improves.
COPYRIGHT: (C)1979,JPO&Japio
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6467678A JPS54155770A (en) | 1978-05-29 | 1978-05-29 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6467678A JPS54155770A (en) | 1978-05-29 | 1978-05-29 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS54155770A true JPS54155770A (en) | 1979-12-08 |
Family
ID=13265003
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6467678A Pending JPS54155770A (en) | 1978-05-29 | 1978-05-29 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS54155770A (en) |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56169319A (en) * | 1980-05-30 | 1981-12-26 | Nec Home Electronics Ltd | Manufacture of semiconductor device |
| US5063177A (en) * | 1990-10-04 | 1991-11-05 | Comsat | Method of packaging microwave semiconductor components and integrated circuits |
| US6500694B1 (en) | 2000-03-22 | 2002-12-31 | Ziptronix, Inc. | Three dimensional device integration method and integrated device |
| US7023051B2 (en) | 2003-04-29 | 2006-04-04 | Micron Technology, Inc. | Localized strained semiconductor on insulator |
| US7041178B2 (en) | 2000-02-16 | 2006-05-09 | Ziptronix, Inc. | Method for low temperature bonding and bonded structure |
| US7045874B2 (en) | 2003-05-07 | 2006-05-16 | Micron Technology, Inc. | Micromechanical strained semiconductor by wafer bonding |
| US7084429B2 (en) | 2003-04-29 | 2006-08-01 | Micron, Technology, Inc. | Strained semiconductor by wafer bonding with misorientation |
| US7198974B2 (en) * | 2003-03-05 | 2007-04-03 | Micron Technology, Inc. | Micro-mechanically strained semiconductor film |
| US8962447B2 (en) | 2006-08-03 | 2015-02-24 | Micron Technology, Inc. | Bonded strained semiconductor with a desired surface orientation and conductance direction |
| US10366962B2 (en) | 1999-10-01 | 2019-07-30 | Invensas Bonding Technologies, Inc. | Three dimensional device integration method and integrated device |
| US11760059B2 (en) | 2003-05-19 | 2023-09-19 | Adeia Semiconductor Bonding Technologies Inc. | Method of room temperature covalent bonding |
-
1978
- 1978-05-29 JP JP6467678A patent/JPS54155770A/en active Pending
Cited By (22)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56169319A (en) * | 1980-05-30 | 1981-12-26 | Nec Home Electronics Ltd | Manufacture of semiconductor device |
| US5063177A (en) * | 1990-10-04 | 1991-11-05 | Comsat | Method of packaging microwave semiconductor components and integrated circuits |
| US10366962B2 (en) | 1999-10-01 | 2019-07-30 | Invensas Bonding Technologies, Inc. | Three dimensional device integration method and integrated device |
| US9331149B2 (en) | 2000-02-16 | 2016-05-03 | Ziptronix, Inc. | Method for low temperature bonding and bonded structure |
| US7041178B2 (en) | 2000-02-16 | 2006-05-09 | Ziptronix, Inc. | Method for low temperature bonding and bonded structure |
| US10312217B2 (en) | 2000-02-16 | 2019-06-04 | Invensas Bonding Technologies, Inc. | Method for low temperature bonding and bonded structure |
| US9391143B2 (en) | 2000-02-16 | 2016-07-12 | Ziptronix, Inc. | Method for low temperature bonding and bonded structure |
| US8053329B2 (en) | 2000-02-16 | 2011-11-08 | Ziptronix, Inc. | Method for low temperature bonding and bonded structure |
| US7335572B2 (en) | 2000-02-16 | 2008-02-26 | Ziptronix, Inc. | Method for low temperature bonding and bonded structure |
| US7387944B2 (en) | 2000-02-16 | 2008-06-17 | Ziptronix, Inc. | Method for low temperature bonding and bonded structure |
| US9082627B2 (en) | 2000-02-16 | 2015-07-14 | Ziptronix, Inc. | Method for low temperature bonding and bonded structure |
| US6627531B2 (en) | 2000-03-22 | 2003-09-30 | Ziptronix, Inc. | Three dimensional device integration method and integrated device |
| US7037755B2 (en) | 2000-03-22 | 2006-05-02 | Ziptronix, Inc. | Three dimensional device integration method and integrated device |
| US6500694B1 (en) | 2000-03-22 | 2002-12-31 | Ziptronix, Inc. | Three dimensional device integration method and integrated device |
| US7198974B2 (en) * | 2003-03-05 | 2007-04-03 | Micron Technology, Inc. | Micro-mechanically strained semiconductor film |
| US7429763B2 (en) | 2003-04-29 | 2008-09-30 | Micron Technology, Inc. | Memory with strained semiconductor by wafer bonding with misorientation |
| US7084429B2 (en) | 2003-04-29 | 2006-08-01 | Micron, Technology, Inc. | Strained semiconductor by wafer bonding with misorientation |
| US7041575B2 (en) | 2003-04-29 | 2006-05-09 | Micron Technology, Inc. | Localized strained semiconductor on insulator |
| US7023051B2 (en) | 2003-04-29 | 2006-04-04 | Micron Technology, Inc. | Localized strained semiconductor on insulator |
| US7045874B2 (en) | 2003-05-07 | 2006-05-16 | Micron Technology, Inc. | Micromechanical strained semiconductor by wafer bonding |
| US11760059B2 (en) | 2003-05-19 | 2023-09-19 | Adeia Semiconductor Bonding Technologies Inc. | Method of room temperature covalent bonding |
| US8962447B2 (en) | 2006-08-03 | 2015-02-24 | Micron Technology, Inc. | Bonded strained semiconductor with a desired surface orientation and conductance direction |
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