JPS54144123A - Pattern generator - Google Patents

Pattern generator

Info

Publication number
JPS54144123A
JPS54144123A JP5207778A JP5207778A JPS54144123A JP S54144123 A JPS54144123 A JP S54144123A JP 5207778 A JP5207778 A JP 5207778A JP 5207778 A JP5207778 A JP 5207778A JP S54144123 A JPS54144123 A JP S54144123A
Authority
JP
Japan
Prior art keywords
counter
output
horizontal
outputting
vertical
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5207778A
Other languages
Japanese (ja)
Inventor
Yukinori Kudo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP5207778A priority Critical patent/JPS54144123A/en
Publication of JPS54144123A publication Critical patent/JPS54144123A/en
Pending legal-status Critical Current

Links

Landscapes

  • Testing, Inspecting, Measuring Of Stereoscopic Televisions And Televisions (AREA)

Abstract

PURPOSE: To observe the horizontal and vertical linearity of TV receivers, by giving the line tilt pattern functions to the simple type pattern generator, and by making easy the evaluation of total linearity of TV screen.
CONSTITUTION: The oscillator 1 outputting the clock pulse 2 integer times the horizontal frequency, the horizontal counter 3 counting the clock pulse 2 of the oscillator 1 and outputting the horizontal frequency signal, and vertical counter 11 counting the specified bit output of the counter 3 and outputting the vertical frequency signal, are provided. Further, the comparator 7 taking the output of the counter 3 as one input, taking the output of the counter 11 as another input, and detecting the agreement, and the comparator 9 detecting the agreement between the inverted input of the counter 3 and the output of the counter 11, are provided. Further, the logical sum of the comparators 7 and 9 is taken with the gate circuit 14, the output of the circuit 14 is fed to the modulator 22, the output of the signal generating and control circuit 20 wich inputs the output of the counters 3 and 11 is controlled to display the line pattern tilt on the CRT.
COPYRIGHT: (C)1979,JPO&Japio
JP5207778A 1978-04-29 1978-04-29 Pattern generator Pending JPS54144123A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5207778A JPS54144123A (en) 1978-04-29 1978-04-29 Pattern generator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5207778A JPS54144123A (en) 1978-04-29 1978-04-29 Pattern generator

Publications (1)

Publication Number Publication Date
JPS54144123A true JPS54144123A (en) 1979-11-10

Family

ID=12904746

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5207778A Pending JPS54144123A (en) 1978-04-29 1978-04-29 Pattern generator

Country Status (1)

Country Link
JP (1) JPS54144123A (en)

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