JPS54139710A - Reproducer of digial signals - Google Patents

Reproducer of digial signals

Info

Publication number
JPS54139710A
JPS54139710A JP4799078A JP4799078A JPS54139710A JP S54139710 A JPS54139710 A JP S54139710A JP 4799078 A JP4799078 A JP 4799078A JP 4799078 A JP4799078 A JP 4799078A JP S54139710 A JPS54139710 A JP S54139710A
Authority
JP
Japan
Prior art keywords
circuit
data
memory
wrong data
memory circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4799078A
Other languages
Japanese (ja)
Other versions
JPS6131548B2 (en
Inventor
Nobuyoshi Kihara
Koji Matsushima
Taiji Shimeki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP4799078A priority Critical patent/JPS54139710A/en
Publication of JPS54139710A publication Critical patent/JPS54139710A/en
Publication of JPS6131548B2 publication Critical patent/JPS6131548B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE: To editing to be performed through cutting of PCM recording tape by jumping the wrong data detected and reading out the next data by the use of a data error detecting circuit and a memory circuit.
CONSTITUTION: Normal reproduction digital input signals are subsequently memorized in a memory circuit 1 based on the period of the clock signal 3 by an address assigning circuit 2. The contents of the memory circuit 1 are subsequently read out in synchronization to the period of the circuit 2 by a read-out address assigning circuit 4. Now, when a wrong data is inputted, it is memorized in the memory circuit 1 and is at the same time detected in a detecting circuit 6. A control circuit 8 causes the circuit 4 to jump the wrong data having been stored in the memory 1 and read out the next normal data. Since this obviates outputting of the wrong data and causes the normal signals to be outputted continuously, reproduction may be performed without production of any noise from the splices of the PCM recorded tape even if it is cut and edited.
COPYRIGHT: (C)1979,JPO&Japio
JP4799078A 1978-04-21 1978-04-21 Reproducer of digial signals Granted JPS54139710A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4799078A JPS54139710A (en) 1978-04-21 1978-04-21 Reproducer of digial signals

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4799078A JPS54139710A (en) 1978-04-21 1978-04-21 Reproducer of digial signals

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP8339178A Division JPS54139709A (en) 1978-07-07 1978-07-07 Reproducer of digital signals

Publications (2)

Publication Number Publication Date
JPS54139710A true JPS54139710A (en) 1979-10-30
JPS6131548B2 JPS6131548B2 (en) 1986-07-21

Family

ID=12790749

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4799078A Granted JPS54139710A (en) 1978-04-21 1978-04-21 Reproducer of digial signals

Country Status (1)

Country Link
JP (1) JPS54139710A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61184769A (en) * 1985-02-12 1986-08-18 Sony Corp Digital signal processor
JPS61502577A (en) * 1984-06-01 1986-11-06 テレフンケン フエルンゼ− ウント ルントフンク ゲゼルシヤフト ミツト ベシユレンクテル ハフツング Method for reducing sensitivity to errors in digital audio signals
JPH0531396U (en) * 1984-06-01 1993-04-23 テレフンケン フエルンゼー ウント ルントフンク ゲゼルシヤフト ミツト ベシユレンクテル ハフツング Receiver for reception of audio and / or video signals

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61502577A (en) * 1984-06-01 1986-11-06 テレフンケン フエルンゼ− ウント ルントフンク ゲゼルシヤフト ミツト ベシユレンクテル ハフツング Method for reducing sensitivity to errors in digital audio signals
JPH0531396U (en) * 1984-06-01 1993-04-23 テレフンケン フエルンゼー ウント ルントフンク ゲゼルシヤフト ミツト ベシユレンクテル ハフツング Receiver for reception of audio and / or video signals
JPS61184769A (en) * 1985-02-12 1986-08-18 Sony Corp Digital signal processor

Also Published As

Publication number Publication date
JPS6131548B2 (en) 1986-07-21

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