JPS54132135A - Memory control unit - Google Patents

Abstract

PURPOSE:To avoid mis writing of the input data as well as to reduce the memory capacity by dividing the frame or the field memory into 4 memory blocks MB and then writing the input signals into the MB with every unit length. CONSTITUTION:Frame or field memory part 6 is divided into 4 units of MB6A- 6D, and input buffer circuits 5A-5D are provided at the input sides of MB6A-6D to give the series-parallel conversion to the input digital signals. The capacity of circuits 5A-5D is selected to the writing capacity equivalent to one memory cycle MC of MB, and the signals are written into MB in synchronization with MC in sequence at the end of writing of 5A-5D. At the same time, if the writing takes place to different MB's within the same MC, the simultaneous writing is given to those MB's. The signals read out from MB are supplied with every second one to parallel-series conversion output buffer 11A and 11B provided in common. And the execution timing is secured via write/read control circuit 16 and with synchronous coupling to the phase of the reference station in the key station. Thus, the miswriting of the data caused by the nonsynchronization between the input and output can be prevented effectively.