JPS54117645A - Buffer memory control system - Google Patents

Buffer memory control system

Info

Publication number
JPS54117645A
JPS54117645A JP2465478A JP2465478A JPS54117645A JP S54117645 A JPS54117645 A JP S54117645A JP 2465478 A JP2465478 A JP 2465478A JP 2465478 A JP2465478 A JP 2465478A JP S54117645 A JPS54117645 A JP S54117645A
Authority
JP
Japan
Prior art keywords
data block
address
buffer memory
control part
transmission
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2465478A
Other languages
Japanese (ja)
Other versions
JPS5719804B2 (en
Inventor
Yoshio Inui
Eiou Yamauchi
Takenori Endo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Nippon Telegraph and Telephone Corp
Oki Electric Industry Co Ltd
Original Assignee
NEC Corp
Nippon Telegraph and Telephone Corp
Oki Electric Industry Co Ltd
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Telegraph and Telephone Corp, Oki Electric Industry Co Ltd, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP2465478A priority Critical patent/JPS54117645A/en
Publication of JPS54117645A publication Critical patent/JPS54117645A/en
Publication of JPS5719804B2 publication Critical patent/JPS5719804B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE: To improve the use efficiency of a buffer memory by stopping immediately the transmission/receiving processing of a data block where a fault occurrs and making it possible to restart the transmission/receiving processing of the next data block.
CONSTITUTION: In case that line control part 202 detects anomaly occurrence in the receiving operation, the receiving operation of the block is stopped to restart to store the next data block from the next address. Meanwhile, in case that control part 202 detects anomaly occurrence in the transmission operation, executing address 303 is corrected to set the start address of the data block if one data block write completion indication 304 is set by interface control part 200; and executing addresses 302 and 303 are caused to agree with each other forcedly to set this address as the start address of the data block if the final address has not been set yet. As a result, the needless processing at an anomaly occurrence time is eliminated to be able to improve the use efficiency of the buffer memory.
COPYRIGHT: (C)1979,JPO&Japio
JP2465478A 1978-03-03 1978-03-03 Buffer memory control system Granted JPS54117645A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2465478A JPS54117645A (en) 1978-03-03 1978-03-03 Buffer memory control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2465478A JPS54117645A (en) 1978-03-03 1978-03-03 Buffer memory control system

Publications (2)

Publication Number Publication Date
JPS54117645A true JPS54117645A (en) 1979-09-12
JPS5719804B2 JPS5719804B2 (en) 1982-04-24

Family

ID=12144120

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2465478A Granted JPS54117645A (en) 1978-03-03 1978-03-03 Buffer memory control system

Country Status (1)

Country Link
JP (1) JPS54117645A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59165610U (en) * 1983-04-21 1984-11-06 三菱電機株式会社 fluorescent light

Also Published As

Publication number Publication date
JPS5719804B2 (en) 1982-04-24

Similar Documents

Publication Publication Date Title
JPS564862A (en) Computer system
JPS55105897A (en) Memory device
JPS5533232A (en) Sequential controller
JPS5344134A (en) Microprogram control system
JPS5580158A (en) False fault generation control system
JPS54117645A (en) Buffer memory control system
JPS5259537A (en) Data processor
JPS5324743A (en) Bus selector for electronic computer
JPS556608A (en) Computer restart system
JPS57159350A (en) System correction and processing system in system operation
JPS5544662A (en) Input/output program control unit
JPS5776604A (en) Numeric controller
JPS55131853A (en) Control method for multiple-system electronic computer
JPS51127637A (en) Information processing device under micro program control system
JPS54151331A (en) Data processor
JPS57199052A (en) Data processing device
JPS5352329A (en) Electronic computer
JPS54115036A (en) Control system for microprogram
JPS5525820A (en) Buffer memory device
JPS55162156A (en) Data processor
JPS55901A (en) Data buffer control system
JPS567152A (en) Address stopping system for arithmetic process system
JPS5468133A (en) Address self restoration unit of computer system
JPS5378745A (en) Composing system of control memory
JPS5532208A (en) Memory control system