JPS54116888A - Manufacture of dielectric separate substrate - Google Patents
Manufacture of dielectric separate substrateInfo
- Publication number
- JPS54116888A JPS54116888A JP2353678A JP2353678A JPS54116888A JP S54116888 A JPS54116888 A JP S54116888A JP 2353678 A JP2353678 A JP 2353678A JP 2353678 A JP2353678 A JP 2353678A JP S54116888 A JPS54116888 A JP S54116888A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- semiconductor
- manufacture
- island
- sio
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Element Separation (AREA)
Abstract
PURPOSE: To manufacture a semiconductor substrate separated by a dielectric by making the size of a support substrate larger than that of a semiconductor single- crystal substrate.
CONSTITUTION: Both (n)-type Si substrates 110 and 210 are used and covered with SiO2 130. Substrate 110 is provided for anisotropic etching with separating groove 120, which is covered with SiO2 and poly-Si 140. Next, BSG 150 is stacked on both the substrates and both lamination surfaces are made in contact and pressed in N2 at 1250°C for sixty minutes, thereby forming a bonded body. Then, substrate 110 is polished to a thickness of approximate 50μm, so that island 110a of the insulation separate semiconductor can be obtained. On this island, (p) layer 160n, layer 170, protective film 180, electrode 190, etc., are formed. When the diameter of supporting substrate 210 is 3mm longer than that of the semiconductor substrate, the substrate will never by damaged in a polishing process and others.
COPYRIGHT: (C)1979,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2353678A JPS54116888A (en) | 1978-03-03 | 1978-03-03 | Manufacture of dielectric separate substrate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2353678A JPS54116888A (en) | 1978-03-03 | 1978-03-03 | Manufacture of dielectric separate substrate |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS54116888A true JPS54116888A (en) | 1979-09-11 |
Family
ID=12113174
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2353678A Pending JPS54116888A (en) | 1978-03-03 | 1978-03-03 | Manufacture of dielectric separate substrate |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS54116888A (en) |
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57180148A (en) * | 1981-04-30 | 1982-11-06 | Fujitsu Ltd | Manufacture of semiconductor device having dielectric isolation structure |
JPS61292934A (en) * | 1985-06-21 | 1986-12-23 | Toshiba Corp | Manufacture of semiconductor element |
JPS6489346A (en) * | 1987-09-29 | 1989-04-03 | Sony Corp | Semiconductor substrate |
US5063177A (en) * | 1990-10-04 | 1991-11-05 | Comsat | Method of packaging microwave semiconductor components and integrated circuits |
US5064771A (en) * | 1990-04-13 | 1991-11-12 | Grumman Aerospace Corporation | Method of forming crystal array |
US5231045A (en) * | 1988-12-08 | 1993-07-27 | Fujitsu Limited | Method of producing semiconductor-on-insulator structure by besol process with charged insulating layers |
JPH08264637A (en) * | 1995-03-23 | 1996-10-11 | Ube Ind Ltd | Composite semiconductor substrate |
JPH08264636A (en) * | 1995-03-23 | 1996-10-11 | Ube Ind Ltd | Composite semiconductor substrate |
US6500694B1 (en) | 2000-03-22 | 2002-12-31 | Ziptronix, Inc. | Three dimensional device integration method and integrated device |
US7041178B2 (en) | 2000-02-16 | 2006-05-09 | Ziptronix, Inc. | Method for low temperature bonding and bonded structure |
US10366962B2 (en) | 1999-10-01 | 2019-07-30 | Invensas Bonding Technologies, Inc. | Three dimensional device integration method and integrated device |
US11760059B2 (en) | 2003-05-19 | 2023-09-19 | Adeia Semiconductor Bonding Technologies Inc. | Method of room temperature covalent bonding |
-
1978
- 1978-03-03 JP JP2353678A patent/JPS54116888A/en active Pending
Cited By (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57180148A (en) * | 1981-04-30 | 1982-11-06 | Fujitsu Ltd | Manufacture of semiconductor device having dielectric isolation structure |
JPS61292934A (en) * | 1985-06-21 | 1986-12-23 | Toshiba Corp | Manufacture of semiconductor element |
JPS6489346A (en) * | 1987-09-29 | 1989-04-03 | Sony Corp | Semiconductor substrate |
JP2535957B2 (en) * | 1987-09-29 | 1996-09-18 | ソニー株式会社 | Semiconductor substrate |
US5231045A (en) * | 1988-12-08 | 1993-07-27 | Fujitsu Limited | Method of producing semiconductor-on-insulator structure by besol process with charged insulating layers |
US5064771A (en) * | 1990-04-13 | 1991-11-12 | Grumman Aerospace Corporation | Method of forming crystal array |
US5063177A (en) * | 1990-10-04 | 1991-11-05 | Comsat | Method of packaging microwave semiconductor components and integrated circuits |
JPH08264637A (en) * | 1995-03-23 | 1996-10-11 | Ube Ind Ltd | Composite semiconductor substrate |
JPH08264636A (en) * | 1995-03-23 | 1996-10-11 | Ube Ind Ltd | Composite semiconductor substrate |
US10366962B2 (en) | 1999-10-01 | 2019-07-30 | Invensas Bonding Technologies, Inc. | Three dimensional device integration method and integrated device |
US8053329B2 (en) | 2000-02-16 | 2011-11-08 | Ziptronix, Inc. | Method for low temperature bonding and bonded structure |
US7041178B2 (en) | 2000-02-16 | 2006-05-09 | Ziptronix, Inc. | Method for low temperature bonding and bonded structure |
US7335572B2 (en) | 2000-02-16 | 2008-02-26 | Ziptronix, Inc. | Method for low temperature bonding and bonded structure |
US7387944B2 (en) | 2000-02-16 | 2008-06-17 | Ziptronix, Inc. | Method for low temperature bonding and bonded structure |
US9082627B2 (en) | 2000-02-16 | 2015-07-14 | Ziptronix, Inc. | Method for low temperature bonding and bonded structure |
US9331149B2 (en) | 2000-02-16 | 2016-05-03 | Ziptronix, Inc. | Method for low temperature bonding and bonded structure |
US9391143B2 (en) | 2000-02-16 | 2016-07-12 | Ziptronix, Inc. | Method for low temperature bonding and bonded structure |
US10312217B2 (en) | 2000-02-16 | 2019-06-04 | Invensas Bonding Technologies, Inc. | Method for low temperature bonding and bonded structure |
US7037755B2 (en) | 2000-03-22 | 2006-05-02 | Ziptronix, Inc. | Three dimensional device integration method and integrated device |
US6627531B2 (en) | 2000-03-22 | 2003-09-30 | Ziptronix, Inc. | Three dimensional device integration method and integrated device |
US6500694B1 (en) | 2000-03-22 | 2002-12-31 | Ziptronix, Inc. | Three dimensional device integration method and integrated device |
US11760059B2 (en) | 2003-05-19 | 2023-09-19 | Adeia Semiconductor Bonding Technologies Inc. | Method of room temperature covalent bonding |
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