JPS54111733A - Multiplex processor system - Google Patents

Multiplex processor system

Info

Publication number
JPS54111733A
JPS54111733A JP1928678A JP1928678A JPS54111733A JP S54111733 A JPS54111733 A JP S54111733A JP 1928678 A JP1928678 A JP 1928678A JP 1928678 A JP1928678 A JP 1928678A JP S54111733 A JPS54111733 A JP S54111733A
Authority
JP
Japan
Prior art keywords
task
control section
processor
control
sections
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1928678A
Other languages
Japanese (ja)
Other versions
JPS5744174B2 (en
Inventor
Naoaki Yasumi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP1928678A priority Critical patent/JPS54111733A/en
Publication of JPS54111733A publication Critical patent/JPS54111733A/en
Publication of JPS5744174B2 publication Critical patent/JPS5744174B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Hardware Redundancy (AREA)
  • Multi Processors (AREA)

Abstract

PURPOSE: To increase the ratio of cost to performance, by executing the task represented for the priority having the highest priority by the processor designated with the processor designated information.
CONSTITUTION: The system consists of the main memory 1, first and second processor 2, 3, and input and output channel unit 4 connected to I/O 5, and the process control block information used for the control of processor usage right is stored in the unit 1. Further, the porcessor 2 consists of the sequential control section 31, interruption control section 32, semaphore control section 33, control section 34 selecting the task to be executed, memory access circuit 35, operation circuit 36 and register 37, and control sections 31 and 32 requests the start of the control operation with the control section 34 while relating to the contrl sections 33, and if there is no task under execution with the processor 2, the task having the highest priority among the task group possible for execution is found and the task corresponding is out of linkage from the queue by rolling in it.
COPYRIGHT: (C)1979,JPO&Japio
JP1928678A 1978-02-21 1978-02-21 Multiplex processor system Granted JPS54111733A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1928678A JPS54111733A (en) 1978-02-21 1978-02-21 Multiplex processor system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1928678A JPS54111733A (en) 1978-02-21 1978-02-21 Multiplex processor system

Publications (2)

Publication Number Publication Date
JPS54111733A true JPS54111733A (en) 1979-09-01
JPS5744174B2 JPS5744174B2 (en) 1982-09-20

Family

ID=11995196

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1928678A Granted JPS54111733A (en) 1978-02-21 1978-02-21 Multiplex processor system

Country Status (1)

Country Link
JP (1) JPS54111733A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56110154A (en) * 1980-02-06 1981-09-01 Fuji Xerox Co Ltd Sequence control system by microcomputer
JPS56124964A (en) * 1979-12-11 1981-09-30 Cii Device for assigning andsynchronizing execution proposed process between plural processing units for information processor
JPS57500444A (en) * 1980-02-28 1982-03-11
JPS57197652A (en) * 1981-05-22 1982-12-03 Data General Corp Digital data processing system
JPS57206968A (en) * 1981-06-16 1982-12-18 Ibm Process dispatch system
JPS58117054A (en) * 1981-12-29 1983-07-12 Fujitsu Ltd Selecting system for processor
JPS6081650A (en) * 1983-07-21 1985-05-09 バロ−ス・コ−ポレ−シヨン Method of synthesizing sequence and data processing system
JPS6486246A (en) * 1987-09-28 1989-03-30 Nec Corp Task scheduling system

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5023949A (en) * 1973-06-27 1975-03-14
JPS513146A (en) * 1974-06-24 1976-01-12 Nippon Electric Co
JPS5296836A (en) * 1976-02-10 1977-08-15 Toshiba Corp Multiplex data processing system

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5023949A (en) * 1973-06-27 1975-03-14
JPS513146A (en) * 1974-06-24 1976-01-12 Nippon Electric Co
JPS5296836A (en) * 1976-02-10 1977-08-15 Toshiba Corp Multiplex data processing system

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56124964A (en) * 1979-12-11 1981-09-30 Cii Device for assigning andsynchronizing execution proposed process between plural processing units for information processor
JPS56110154A (en) * 1980-02-06 1981-09-01 Fuji Xerox Co Ltd Sequence control system by microcomputer
JPS6342292B2 (en) * 1980-02-06 1988-08-23 Fuji Xerox Co Ltd
JPS57500444A (en) * 1980-02-28 1982-03-11
JPS57197652A (en) * 1981-05-22 1982-12-03 Data General Corp Digital data processing system
JPS57206968A (en) * 1981-06-16 1982-12-18 Ibm Process dispatch system
JPS58117054A (en) * 1981-12-29 1983-07-12 Fujitsu Ltd Selecting system for processor
JPS6081650A (en) * 1983-07-21 1985-05-09 バロ−ス・コ−ポレ−シヨン Method of synthesizing sequence and data processing system
JPH0535454B2 (en) * 1983-07-21 1993-05-26 Unisys Corp
JPS6486246A (en) * 1987-09-28 1989-03-30 Nec Corp Task scheduling system

Also Published As

Publication number Publication date
JPS5744174B2 (en) 1982-09-20

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