JPS54102937A - Information processor - Google Patents

Information processor

Info

Publication number
JPS54102937A
JPS54102937A JP949978A JP949978A JPS54102937A JP S54102937 A JPS54102937 A JP S54102937A JP 949978 A JP949978 A JP 949978A JP 949978 A JP949978 A JP 949978A JP S54102937 A JPS54102937 A JP S54102937A
Authority
JP
Japan
Prior art keywords
idx
microorder
execution
information processor
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP949978A
Other languages
Japanese (ja)
Other versions
JPS6110857B2 (en
Inventor
Masahiro Kuriyama
Hiroshi Takada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP949978A priority Critical patent/JPS54102937A/en
Publication of JPS54102937A publication Critical patent/JPS54102937A/en
Publication of JPS6110857B2 publication Critical patent/JPS6110857B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE: To enhance the performance of the information processor greatly by installing the means which checks the contents of the operation code part within the microorder and the index modification part to memorize the results of the checking plus the subroutine means which carries out the microorder.
CONSTITUTION: The microorder read out from main memory 1 is set to microorder register 2 and then decoded through the decoder circuit. At the same time, the contents are decided at checking circuit 5 for both operation code part 3 and index modification IDX part 4 to give the identification for IDX. In case the execution of IDX is decided, circuit 5 delivers 1. At this instant, gate 7 is opened with timing t1 to set IDXFF6. On the other hand, in case condition signal COND to check the possibility for execution of IDX, the trap signal is transmitted via gate 8 when FF6 is on to be then branched off to the fixed address where the subroutine for execution of IDX is stored. Thus, IDX is carried out. As a result, the performance of the information processor can be enhanced with reduction of the control memory.
COPYRIGHT: (C)1979,JPO&Japio
JP949978A 1978-01-31 1978-01-31 Information processor Granted JPS54102937A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP949978A JPS54102937A (en) 1978-01-31 1978-01-31 Information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP949978A JPS54102937A (en) 1978-01-31 1978-01-31 Information processor

Publications (2)

Publication Number Publication Date
JPS54102937A true JPS54102937A (en) 1979-08-13
JPS6110857B2 JPS6110857B2 (en) 1986-03-31

Family

ID=11721919

Family Applications (1)

Application Number Title Priority Date Filing Date
JP949978A Granted JPS54102937A (en) 1978-01-31 1978-01-31 Information processor

Country Status (1)

Country Link
JP (1) JPS54102937A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6079431A (en) * 1983-10-06 1985-05-07 Hitachi Ltd Programmable controller

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6079431A (en) * 1983-10-06 1985-05-07 Hitachi Ltd Programmable controller
JPH024010B2 (en) * 1983-10-06 1990-01-25 Hitachi Ltd

Also Published As

Publication number Publication date
JPS6110857B2 (en) 1986-03-31

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