JPS53105139A - Dynamic main memory controller - Google Patents

Dynamic main memory controller

Info

Publication number
JPS53105139A
JPS53105139A JP1996277A JP1996277A JPS53105139A JP S53105139 A JPS53105139 A JP S53105139A JP 1996277 A JP1996277 A JP 1996277A JP 1996277 A JP1996277 A JP 1996277A JP S53105139 A JPS53105139 A JP S53105139A
Authority
JP
Japan
Prior art keywords
main memory
memory controller
dynamic main
memory unit
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1996277A
Other languages
Japanese (ja)
Inventor
Hideo Morisue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP1996277A priority Critical patent/JPS53105139A/en
Publication of JPS53105139A publication Critical patent/JPS53105139A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To make it possible to use the specific region of a main memory unit efficiently, by comparing the address of a CPU which is requesting access with the one stored in an address information memory circuit and by causing access to the main memory unit only in case of a discordance.
COPYRIGHT: (C)1978,JPO&Japio
JP1996277A 1977-02-24 1977-02-24 Dynamic main memory controller Pending JPS53105139A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1996277A JPS53105139A (en) 1977-02-24 1977-02-24 Dynamic main memory controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1996277A JPS53105139A (en) 1977-02-24 1977-02-24 Dynamic main memory controller

Publications (1)

Publication Number Publication Date
JPS53105139A true JPS53105139A (en) 1978-09-13

Family

ID=12013811

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1996277A Pending JPS53105139A (en) 1977-02-24 1977-02-24 Dynamic main memory controller

Country Status (1)

Country Link
JP (1) JPS53105139A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5856057A (en) * 1981-09-29 1983-04-02 Nec Corp Interruption signal generating device
JPH01502628A (en) * 1987-05-01 1989-09-07 ディジタル　イクイプメント　コーポレーション Method and apparatus for initiating transactions in a multiprocessor computer system using multiple lock instructions
JPH02500550A (en) * 1987-05-01 1990-02-22 ディジタル　イクイプメント　コーポレーション Method and apparatus for managing multiple lock indicators in a multiprocessor computer system
JPH02500783A (en) * 1987-05-01 1990-03-15 ディジタル　イクイプメント　コーポレーション A device that executes interlock read command messages from the commander node on the responder node.
JP2015530679A (en) * 2012-10-04 2015-10-15 クゥアルコム・インコーポレイテッドＱｕａｌｃｏｍｍ Ｉｎｃｏｒｐｏｒａｔｅｄ Method and apparatus using high efficiency atomic operations

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5856057A (en) * 1981-09-29 1983-04-02 Nec Corp Interruption signal generating device
JPH01502628A (en) * 1987-05-01 1989-09-07 ディジタル　イクイプメント　コーポレーション Method and apparatus for initiating transactions in a multiprocessor computer system using multiple lock instructions
JPH02500550A (en) * 1987-05-01 1990-02-22 ディジタル　イクイプメント　コーポレーション Method and apparatus for managing multiple lock indicators in a multiprocessor computer system
JPH02500783A (en) * 1987-05-01 1990-03-15 ディジタル　イクイプメント　コーポレーション A device that executes interlock read command messages from the commander node on the responder node.
JPH0587855B2 (en) * 1987-05-01 1993-12-20 Digital Equipment Corp
JP2015530679A (en) * 2012-10-04 2015-10-15 クゥアルコム・インコーポレイテッドＱｕａｌｃｏｍｍ Ｉｎｃｏｒｐｏｒａｔｅｄ Method and apparatus using high efficiency atomic operations

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